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An AMBA-Compliant, Radiation Tolerant Tensor Core for Use in A.I. Applications

Award Information
Agency: National Aeronautics and Space Administration
Branch: N/A
Contract: 80NSSC18P2222
Agency Tracking Number: 181872
Amount: $124,931.00
Phase: Phase I
Program: SBIR
Solicitation Topic Code: Z8
Solicitation Number: SBIR_18_P1
Solicitation Year: 2018
Award Year: 2018
Award Start Date (Proposal Award Date): 2018-07-27
Award End Date (Contract End Date): 2019-02-15
Small Business Information
4775 Centennial Boulevard, Suite 130
Colorado Springs, CO 80919-3332
United States
DUNS: 619085371
HUBZone Owned: No
Woman Owned: No
Socially and Economically Disadvantaged: No
Principal Investigator
 Brent Moss
 (719) 531-0805
Business Contact
 Karen Van Cura
Phone: (719) 531-0805
Research Institution

A novel data processing accelerator intellectual property (IP) Radiation-Hardened-by-Design (RHBD) core for use in NASA future missions is proposed. The core is an artificial neural network accelerator based upon work done at Google, IBM, and others. The IP core is known as a tensor core and follows an architecture of matrix multipliers, accumulators, register files, and fast and abundant memory access. The tensor core will be developed to be Advanced Microcontroller Bus Architecture (AMBA) bus compliant and will feature an architectural approach to easily expand the data processing elements when more die area is available. The core will be developed on the trusted Global Foundries (GF) 32nm Silicon on Insulator (SOI) process. There is extensive development currently occurring at this process technology, including NASA’s future High Performance Spaceflight Computing (HPSC) platform. The core is proposed as an effort to develop a data processing acceleration to decrease the down-link data bandwidth of future space missions. If more processing can be accomplished in situ, a given mission can be expected to require less data bandwidth, a problem that is becoming more critical with the ever increasing number of active missions. The IP core will be developed to be incorporated into other development at the 32nm process. The IP core will also be structured in such a way as to be incorporated into Micro-RDC’s future Reticle Programmable System on Chip (RPSoC) platform. The RPSoC is an active future platform, under development with funding from NASA and the Air Force, for digital and mixed signal designs to lower the cost of development at 32nm and to decrease lead-time from design inception to product delivery. The tensor core will be featured on this platform as a data acceleration core. The core will have RHBD techniques throughout the FEOL and BEOL to ensure that no data will be corrupted within the artificial neural network configuration or the data path.

* Information listed above is at the time of submission. *

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