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Data Converter Systems on Chip

Award Information
Agency: Department of Defense
Branch: Army
Contract: W15QKN-19-P-0017
Agency Tracking Number: A181-009-0743
Amount: $99,999.01
Phase: Phase I
Program: SBIR
Solicitation Topic Code: A18-009
Solicitation Number: 2018.1
Solicitation Year: 2018
Award Year: 2019
Award Start Date (Proposal Award Date): 2018-10-24
Award End Date (Contract End Date): 2019-04-22
Small Business Information
4568 South Highland Drive, Salt Lake City, UT, 84117
DUNS: 831704874
HUBZone Owned: N
Woman Owned: N
Socially and Economically Disadvantaged: N
Principal Investigator
 Dr. Kent Smith
 (801) 891-8785
Business Contact
 Thomas Wolf
Phone: (801) 913-4332
Research Institution
Silicon Technologies will design and simulate in Verilog-AMS and Cadence Spectre an ADC, two DACs, a serial interface and other circuits to be built on a single chip in a ITAR complaint manufacturing process.The ARMY is interested in this development for use in a SWAP-C ASIC for next generation fuse proximity sensors and other programs.STI proposes to use an existing pipelined ADC that has been built both as a stand-alone 0.9V, 100MSPS, and 12-bits ADC and as part of a System on a Chip (SOC) with Northrop Grumman Aerospace systems.STI will modify this existing design to run at 3.3V, 20MSPS, and 12-bits.The two DACs, the serial interface and other circuits will be modifications of proven existing designs. To minimize design and layout time, STI shall use its ADONIS Analog Cell Library built in the DARPA CRAFT program.The cell set contains the basic components required for the design of the ADC including single transistors, multiple groups of single transistors, hierarchical cells such as operational amplifiers, bias generators, voltage references, resistors and capacitors.This new proprietary design technology puts STI in a unique position to satisfy the requirements for this program.

* Information listed above is at the time of submission. *

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