Digital Pixel Sensor with Efficient On-Chip Data Compression

This proposal outlines a very high dynamic range large-format small-pitch low-power digital pixel readout integrated circuit (DPROIC) for infrared focal plane arrays and will be designed to support an entire family of formats. This DPROIC will have on-chip compression for efficient transmission of data on large format, fast data rate sensors. This digital pixel readout will be a complete camera-on-chip architecture when combined with an SLS detectors in a hybrid fashion. It will also operate over a wide range from cryogenic to room temperature to support a broad range of detector architectures. The proposed DPROIC will be implemented in a mature CMOS process with much more reasonable mask costs as compared to that of state-of-the-art line width processes, saving the government money and broadening the possible supplier base. The final product will be flexible enough to be used as a generic readout integrated circuit for a broad range of Army and US Government applications.