Advanced High Operating Temperature Mid-Wave Infrared Sensors

Award Information
Agency:
Department of Defense
Branch
Army
Amount:
$69,991.00
Award Year:
2005
Program:
SBIR
Phase:
Phase I
Contract:
W911QX-06-C-0021
Award Id:
73898
Agency Tracking Number:
A052-052-0738
Solicitation Year:
n/a
Solicitation Topic Code:
n/a
Solicitation Number:
n/a
Small Business Information
EPIR TECHNOLOGIES, INC. (Currently EPIR Technologies Inc )
590 Territorial Drive, Suite B, Bolingbrook, IL, 60440
Hubzone Owned:
N
Minority Owned:
N
Woman Owned:
N
Duns:
068568588
Principal Investigator:
Silviu Velicu
Senior Engineer
(630) 771-0203
svelicu@epir.com
Business Contact:
Sivalingam Sivananthan
President
(630) 771-0201
siva@epir.com
Research Institution:
n/a
Abstract
High sensitivity HgCdTe infrared arrays operating at 77K can now be tailored in a wide range of wavelengths. However, the cooling requirements make them bulky and unsuitable for many DOD applications. We propose two novel approaches to increase their operating temperature. In the first approach, we will demonstrate p-d-n equilibrium HgCdTe detectors. Because of the lack of symmetry between the valence and conduction bands in HgCdTe, the lifetimes in d-type material are higher than those in n-type layers. The challenge of implementing a p-d-n HgCdTe detector is to obtain low p-type doping in the absorber region. Arsenic will be introduced by a novel technique based on implantation and diffusion by thermal annealing. In the second approach, p-d-n devices developed in the first approach will be operated under non-equilibrium conditions. In non-equilibrium operation the minority carriers are extracted to one side of the active area of a detector and the contact to the other side prevents their replenishment. As a consequence, the carrier concentration is decreased dramatically. This leads to increases in recombination lifetimes, dynamic impedances and detectivities. To implement these two approaches, we propose to use HgCdTe infrared materials grown by molecular beam epitaxy (MBE) directly on large area (3-5") silicon substrates with CdTe buffer layers.

* information listed above is at the time of submission.

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