Copper Nano-TSVs for 3D Integrated Sensors

Award Information
Agency: Department of Energy
Branch: N/A
Contract: DE-SC0019528
Agency Tracking Number: 242708
Amount: $149,930.72
Phase: Phase I
Program: SBIR
Solicitation Topic Code: 29d
Solicitation Number: DE-FOA-0001940
Timeline
Solicitation Year: 2019
Award Year: 2019
Award Start Date (Proposal Award Date): 2019-02-19
Award End Date (Contract End Date): 2019-11-18
Small Business Information
1415 Bond Street, Suite 155, Naperville, IL, 60563-2769
DUNS: 080307250
HUBZone Owned: N
Woman Owned: N
Socially and Economically Disadvantaged: N
Principal Investigator
 Robert Patti
 (331) 701-7070
 rpatti@nhanced-semi.com.com
Business Contact
 Robert Patti
Phone: (331) 701-7070
Email: rpatti@nhanced-semi.com.com
Research Institution
N/A
Abstract
3D circuit integration improves performance, reduces cost, and enables new applications by intimate heterogeneous integration of best of class semiconductor devices. A necessary element for 3D assembly is Through Silicon Vias (TSVs), which provide vertical electrical connections in the stacked device. NHanced currently employs tungsten to fill its nanoscale TSVs (0.4 to 1.2µm diameter). Tungsten’s advantages include a low coefficient of expansion (similar to that of silicon) and virtually no electro- migration. Its greatest drawback is that it requires a high deposition temperature (>400°C). For via-first or via-mid TSV insertion, temperature is not an issue. However, we have seen instances of backside via- last TSV insertion where the high temperature of tungsten deposition caused metal migration where the TSV landed. The landing metal (often copper) extruded into the TSV hole during tungsten filling, often breaking through barrier layer materials and creating voids that could cause long term reliability issues. NHanced Semiconductors proposes to develop a via-last process that achieves high yield nano-TSVs (Though Silicon Via) using copper (Cu.) Cu is plated at near room temperature, avoiding the high temperature tungsten issues. However, Cu presents its own challenges. Cu TSVs have been tried with varying success. Years ago, during early 3D development, issues arose due to Cu’s thermal expansion mismatch to silicon. This caused cracked liners and planarity issues during 3D bonding. More recently, these issues have been solved for larger Cu TSVs (2-10µm diameter) like those used in silicon interposers and stacked HBM memory dies. The key is multiple annealing and planarization passes prior to 3D assembly. We believe we can adapt these large-TSV fabrication techniques to our nanoscale TSVs, thus significantly improving the reliability of 3D assemblies using via-last technology. Phase I will develop and demonstrate a baseline Cu fill process for TSVs 1.2µm diameter by 6µm deep. An expected challenge is achieving sufficient barrier and Cu seed sidewall coverage to ensure Cu containment and void-free plating. The sidewall angle and roughness of the TSV hole in the silicon is an important factor in barrier and seed layer coverage; tuning the angle will be a major task. Cu plating speed is another factor. Slower plating speeds usually give the best results, but also cost more by tying up expensive equipment; a balance of speed and void-free TSV fill must be met. Phase II will address improved process margin yield and TSV hole landing. Our technology’s heterogeneous 3D integration allows the ROIC layer to be built in any advanced technology node, even those that have no support for via-first or via-mid. The result will be much higher resolution, smaller footprint, and lower cost. 3D integration provides plentiful interconnect, higher speed, and lower power. These advantages are relevant to the high energy physics community in particle trackers and other experiments. In the future, the technology will benefit commercial applications such as digital X-rays and PET scanners.

* Information listed above is at the time of submission. *

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