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Photonic-Storage Subsystem Input/Output (P-SSIO) Interface

Award Information
Agency: Department of Energy
Branch: N/A
Contract: DE-SC0018470
Agency Tracking Number: 243899
Amount: $1,499,846.00
Phase: Phase II
Program: SBIR
Solicitation Topic Code: 05a
Solicitation Number: DE-FOA-0001975
Solicitation Year: 2019
Award Year: 2019
Award Start Date (Proposal Award Date): 2019-05-28
Award End Date (Contract End Date): 2021-05-27
Small Business Information
41 Aero CamiNo
Goleta, CA 93117-3014
United States
DUNS: 191741292
HUBZone Owned: No
Woman Owned: No
Socially and Economically Disadvantaged: No
Principal Investigator
 Leif Johansson
 (805) 967-4900
Business Contact
 Kristin Snyder
Phone: (805) 967-4900
Research Institution

The diverse workload of ever-increasing cloud and high-performance computing applications brings many challenges to traditional server-centric computing system architectures with a fixed amount of compute, memory and storage nodes. Conventional electrical interconnect approach suffers from the incapability of disaggregating the storage from the compute over few meters due to the inherent losses associated with transmitting the high bandwidth electrical signals over long distances. Furthermore, power consumption grows dramatically with high I/O and peripheral bandwidth capacity required by high-performance computing systems limiting systems with electrical interconnects as currently deployed. A more power-efficient reconfigurable interconnect fabric is required to deliver the bandwidth capacity for today’s applications that use PCIe-based storage and require high I/O rates. The objective of this SBIR effort is to design, fabricate, build and test a photonic based I/O interfaces to provide high bandwidth connectivity between the server class Peripheral Component Interconnect Express (PCIe) controllers and Non-Volatile Memory Express (NVMe) storage subsystem for DOE relevant high-performance computing applications. Freedom Photonics designed and fabricated deliverable tunable laser modules to Columbia University. A design has been generated for a Phase II low-power laser array. Devices are currently in fabrication scheduled to be completed by the end of the Phase I effort. Columbia designed and investigated the overall system architecture, subsystem controller and the testbed, and demonstrated a system testbed with PCIe-based optical links and switch controllers based on a SiP platform. The goal of Phase 2 is to develop a reconfigurable low-power photonic switched storage subsystem. It connects 4 FPGA-based hosts and 8 FPGA- based endpoint storage to establish an 8x8 optical connected network with 512Gb/s aggregated bandwidth. In year 1, a 4x4 photonic-storage network with aggregated bandwidth of 256Gb/s and 8 wavelengths will be established. In year 2, a complete 8x8 photonic-storage controlled by the network controller with 512Gb/s aggregated bandwidth and 16 wavelengths will be demonstrated. The cost and power consumption will be further reduced with the SiP transceiver and laser source integrated with CMOS processor and storage chips. Commercial Applications and Other Benefits: The Photonic Memory Controller developed have wide commercial applications in data center and telecom markets.

* Information listed above is at the time of submission. *

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