SBIR Phase I: A Low Cost Semiconductor Metallization-Planarization Process

Award Information
Agency:
National Science Foundation
Branch
n/a
Amount:
$99,182.00
Award Year:
2001
Program:
SBIR
Phase:
Phase I
Contract:
0060155
Award Id:
52632
Agency Tracking Number:
0060155
Solicitation Year:
n/a
Solicitation Topic Code:
n/a
Solicitation Number:
n/a
Small Business Information
315 Huls Drive, Clayton, OH, 45315
Hubzone Owned:
N
Minority Owned:
N
Woman Owned:
N
Duns:
n/a
Principal Investigator:
E. Jennings Taylor
(937) 836-7749
jennings@erinet.com
Business Contact:
E Jennings Taylor
President
(937) 836-7749
jennings@erinet.com
Research Institute:
n/a
Abstract
This Small Business Innovation Research (SBIR) Phase I project will demonstrate the feasibility of an innovative process for copper metallization and planarization of semiconductor scale features. In contrast to geometric leveling or true leveling in the presence of levelers and brighteners, the proposed electrochemical deposition process is based on charge or Faradaic mediated leveling. The current copper metallization process utilizes a difficult to control plating bath containing levelers and brighteners and generates between 30 and 50 liters of waste slurry for each 8-inch wafer processed. The proposed charge modulated electrochemical deposition process will operate in a simple, easily controlled plating bath and will eliminate or substantially reduce the waste and cost of the current chemical/mechanical-processing step. During the Phase I program, the theoretical basis for the Faradaic mediated leveling process will be established and validated using state-of-the-art ULSI wafers. It is anticipated that the Faradaic mediated leveling process will eliminate or substantially reduce (i.e., by greater than 85%) the copper waste slurry and provide substantial cost savings relevant to the state-of-the-art copper metallization processes in the semiconductor industry

* information listed above is at the time of submission.

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