Open Call for Science and Technology Created by Early-Stage (e.g. University) Teams

Award Information
Agency: Department of Defense
Branch: Air Force
Contract: FA8649-19-P-A076
Agency Tracking Number: F19B-001-0033
Amount: $24,950.00
Phase: Phase I
Program: STTR
Solicitation Topic Code: AF19B-T001
Solicitation Number: 2019.2
Timeline
Solicitation Year: 2019
Award Year: 2019
Award Start Date (Proposal Award Date): 2019-08-02
Award End Date (Contract End Date): 2020-08-02
Small Business Information
5204 E. Ben White Blvd, Austin, TX, 78741
DUNS: 184880446
HUBZone Owned: N
Woman Owned: N
Socially and Economically Disadvantaged: N
Principal Investigator
 Dr. Will Flanagan
 (303) 909-0118
 wflanagan@udallas.edu
Business Contact
 Dr. Tim Hossain
Phone: (512) 934-5331
Email: tim.hossain@ceriumlabs.com
Research Institution
 University of Dallas
 Dr. Jonathan   Sanford
 1845 E Northgate Dr
Irving, TX, 75062
 (972) 721-5388
 Nonprofit college or university
Abstract
Cerium Labs has developed a miniature, highly sensitive, semiconductor device called the Neutron Intercepting Semiconductor Chip (NISC, US Patent 6,075,261) to advance neutron detection technology for national defense. This device is essentially a flash memory chip with a 10B-enriched borophosphosilicate glass (BPSG) layer. The well-known n-10B reaction creates 4He and 7Li particles which deplete charge in the oxide-nitride-oxide layer, flipping the bit from 0 to 1. As this signal is intrinsically digital, there is no signal manipulation or digitization necessary. Furthermore, the active volume and readout of the detector is contained within a single chip allowing an unprecedented scalability, minute form factor, and ease-of-use. Tests of current prototypes have shown high efficiency to neutron radiation and insensitivity to gamma radiation. The NISC detector can work in either an active or passive mode. In passive mode, the chip requires no external power. When turned back on, the number of neutrons detected can be read. Alternatively, active mode operation provides real-time information. Phase I support is solicited for development of an auxiliary board reader, which can scan and reset the memory cells and record timestamps on a continuous basis.

* Information listed above is at the time of submission. *

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