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SBIR Phase II: Chemical Mechanical Planarization pad with controlled micro features for sub 7nm semiconductor technology

Award Information
Agency: National Science Foundation
Branch: N/A
Contract: 1951211
Agency Tracking Number: 1951211
Amount: $977,998.00
Phase: Phase II
Program: SBIR
Solicitation Topic Code: MI
Solicitation Number: N/A
Solicitation Year: 2018
Award Year: 2020
Award Start Date (Proposal Award Date): 2020-04-15
Award End Date (Contract End Date): 2022-03-31
Small Business Information
United States
DUNS: 081229738
HUBZone Owned: No
Woman Owned: No
Socially and Economically Disadvantaged: No
Principal Investigator
 Goo Youn Kim
 (302) 544-2568
Business Contact
 Goo Youn Kim
Phone: (302) 544-2568
Research Institution

The broader impact/commercial potential of this Small Business Innovation Research (SBIR) Phase II project is to help semiconductor chipmakers overcome manufacturing challenges in Chemical Mechanical Planarization/Polishing (CMP) processes. CMP processes enable cutting-edge manufacturing; currently chipmakers often face scaling difficulties as the size of the smallest features continues to decrease, increasing the impact of CMP imperfections and resulting in higher defect rates. The proposed polishing process enables chip fabricators to reduce these CMP imperfections by 50% and improve performance, while reducing costs and increasing process throughput. This Small Business Innovation Research (SBIR) Phase II project will improve CMP processes with innovative polishing pads. Conventional polishing pads have randomly distributed micropores inside of the pads and typically generate around 1% real contact area between the pad asperities and wafer during polishing. This leads to unwanted polishing results, such as dishing/erosion and scratch defects on chip patterns due to the stress concentration on asperities. Conventional pads require a pad conditioning process to regenerate the asperities on the pad surface. The polishing processes developed under this project use microfabrication technologies to control micro-features on the pad surface. Therefore, the contact area between the pad and wafer is customizable and controllable up to 30%. This will improve the polishing performance precision and consistency, leading to fewer defects. As the micro-features on the soft sub-pad are independent, the conformity of the pad increases and the pressure on the wafer is evenly distributed across the wafer surface. This will significantly improve the chip-level planarization and wafer-level uniformity, and reduce the pad wear. As a result, the pad conditioning process can be minimized or even eliminated from the CMP process. This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.

* Information listed above is at the time of submission. *

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