Frontier Technology, Inc.

Award Information
Agency:
Department of Defense
Branch
Navy
Amount:
$69,966.00
Award Year:
1998
Program:
STTR
Phase:
Phase I
Contract:
n/a
Award Id:
40197
Agency Tracking Number:
40197
Solicitation Year:
n/a
Solicitation Topic Code:
n/a
Solicitation Number:
n/a
Small Business Information
4141 Colonel Glenn Highway,, Suite 140, Beavercreek, OH, 45431
Hubzone Owned:
N
Minority Owned:
N
Woman Owned:
N
Duns:
n/a
Principal Investigator:
Gary Key
() -
Business Contact:
Ronald D Shroder
() -
Research Institute:
University of Florida
Sandra Goldstein
219 Grinter Hall
Gainesville, FL, 32611

Nonprofit college or university
Abstract
Digital surveillance of surface and underwater battlefields is complicated by the complexity of the environment, stealth of various threats, and lack of a comprehensive single imaging sensor technology. Therefore, the fusion of multiple sensors inputs of differing type and response characteristics is necessary to achieve coverage in space, time, spectral wavelength and sensing modality. Additionally, the proliferation of high-resolution imaging sensors has resulted in a large data burden that currently grows faster than the increase in processor bandwidth [Sch96a]. In this proposal, we suggest methods for using reconfigurable computing hardware, such as field-programmable gate arrays (FPGA's) or fast, compact SIMD mesh processors to alleviate the computational burden associated with repetitive arithmetic operations. Additionally, we propose to utilize previous and ongoing DoD-funded research at Frontier Technology, Inc., the University of Florida (UF) and the Harbor Branch Oceanographic Institution (HBOI) to render the mapping of target recognition and image processing algorithms more feasible for reconfigurable processors. The expected result is a marriage of UF's expertise and software for architecture-independent algorithm-to-hardware mapping systems with FTI's developments in fast VQ and ATR search paradigms, combined with HBOI's experience with sensor operation, design, development, and performance characterization, to advance reconfigurable computing within near-optimal space, time, and accuracy constraints.

* information listed above is at the time of submission.

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