Array Clocking with Reduced Jitter Using Taped Delay Lines

Award Information
Agency:
Department of Defense
Branch
Navy
Amount:
$69,369.00
Award Year:
2006
Program:
SBIR
Phase:
Phase I
Contract:
N00014-07-M-0062
Award Id:
77008
Agency Tracking Number:
N062-164-0886
Solicitation Year:
n/a
Solicitation Topic Code:
n/a
Solicitation Number:
n/a
Small Business Information
1620 Greenview DR SW, Rochester, MN, 55902
Hubzone Owned:
N
Minority Owned:
N
Woman Owned:
N
Duns:
928507755
Principal Investigator:
JohnWillis
CEO
(507) 288-3154
jwillis@ftlsystems.com
Business Contact:
RuthBetcher
CFO
(507) 288-3154
ruth.betcher@ftlsystems.com
Research Institute:
n/a
Abstract
Deriving coherent antenna array clocks from a common tapped delay line driven by a synchronizing pulse per clock cycle results in reduced jitter and optimal beam forming at minimal cost. Phase one effort analytically considers both electronic and optical implementations with an option for simulation-based validation of a critical PLL circuit and other physical parameters. Analysis considers three clock configurations: 1Ghz with 100FS aperature jitter (per RFP), 21Ghz (2 times X-band) with 50FS jitter and 40GHz (2 times low end of K-band) with 10FS jitter.

* information listed above is at the time of submission.

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