Array Clocking with Reduced Jitter Using Taped Delay Lines

Award Information
Agency: Department of Defense
Branch: Navy
Contract: N00014-07-M-0062
Agency Tracking Number: N062-164-0886
Amount: $99,002.00
Phase: Phase I
Program: SBIR
Awards Year: 2006
Solicitation Year: 2006
Solicitation Topic Code: N06-164
Solicitation Number: 2006.2
Small Business Information
1620 Greenview DR SW, Rochester, MN, 55902
DUNS: 928507755
HUBZone Owned: N
Woman Owned: N
Socially and Economically Disadvantaged: N
Principal Investigator
 John Willis
 CEO
 (507) 288-3154
 jwillis@ftlsystems.com
Business Contact
 Ruth Betcher
Title: CFO
Phone: (507) 288-3154
Email: ruth.betcher@ftlsystems.com
Research Institution
N/A
Abstract
Deriving coherent antenna array clocks from a common tapped delay line driven by a synchronizing pulse per clock cycle results in reduced jitter and optimal beam forming at minimal cost. Phase one effort analytically considers both electronic and optical implementations with an option for simulation-based validation of a critical PLL circuit and other physical parameters. Analysis considers three clock configurations: 1Ghz with 100FS aperature jitter (per RFP), 21Ghz (2 times X-band) with 50FS jitter and 40GHz (2 times low end of K-band) with 10FS jitter.

* Information listed above is at the time of submission. *

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