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Energy-Efficient Reconfigurable Universal Accelerator Interconnect

Award Information
Agency: Department of Energy
Branch: N/A
Contract: DE-SC0019526
Agency Tracking Number: 250328
Amount: $1,499,914.00
Phase: Phase II
Program: SBIR
Solicitation Topic Code: 05a
Solicitation Number: DE-FOA-0002155
Timeline
Solicitation Year: 2020
Award Year: 2020
Award Start Date (Proposal Award Date): 2020-04-06
Award End Date (Contract End Date): 2022-04-05
Small Business Information
1415 Bond Street, Suite 155
Naperville, IL 60563-2769
United States
DUNS: 803072500
HUBZone Owned: No
Woman Owned: No
Socially and Economically Disadvantaged: No
Principal Investigator
 Robert Patti
 (331) 701-7070
 rpatti@nhanced-semi.com
Business Contact
 Robert Patti
Phone: (630) 561-6813
Email: rpatti@nhanced-semi.com
Research Institution
N/A
Abstract

Recent advances in computing systems fundamentally changed and shaped almost every aspect of today’s society; from healthcare to finances and scientific discoveries, our everyday lives will depend more and more on computing and communication infrastructures and their capability to process and deliver critical information in real time. However, as high-performance-computing systems and datacenters already consume megawatts of power, enabling sustainable scaling of future computing systems must consider energy-efficient, parallel, and accelerated heterogeneous processing that can be commercially deployed. The proposed project pursues energy-efficient, high-performance, and universal accelerator interfaces to sustain the ever-increasing demand for scalable and ubiquitous computing processing power. Application domains like high performance computing and machine learning now process data sets of terabytes in size, requiring increasing numbers of processing and memory resources, at the expenses of very high-power consumption due to bottlenecks in the electrical interconnection between processing units. This project aims at significantly reducing the communication energy and latency by developing novel technologies in silicon photonic reconfigurable interconnects to optimally adapt the communication bandwidth and interconnection topology as data flow patterns change for specific application workloads. The research team achieved the following key milestones: (a) fabrication, packaging and testing of an 8-port 16 wavelength reconfigurable all-to-all silicon photonic fabric enabling bandwidth and topology reconfiguration among interconnected nodes; (b) fabrication and testing of low-loss and low-crosstalk integrated optical multiplexers and grating structures for multi-wavelength comb sources; (c) fabrication, packaging and system integration of silicon photonic transceivers bonded with high-speed electronic drivers; (d) assembling a prototype accelerator board for preliminary system testing with all the components fabricated above.For Phase II project, the research team will build upon the milestones achieved in Phase I project to deliver the following key results: (a) 32-wavelength laser with 100GHz spacing; (b) packaged 16-port 32 wavelength reconfigurable all-to-all silicon photonic fabric with electrical control plane for driving the topology and bandwidth reconfiguration between the interconnected nodes; (c) system integration and assembly of accelerator linecards using multi-wavelength electro-optic transceivers and heterogeneous processors; (d) final system demonstration of up to sixteen accelerator linecards interconnected through the fabricated 16-port reconfigurable photonic fabric. The successful completion of this project will lead to significant improvements in energy and performance of large-scale data centers and high-performance computing systems, paving the way for the wide-spread of emerging artificial intelligence applications which are heavily relying on application-specific accelerator units.

* Information listed above is at the time of submission. *

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