Dense Superconducting Memories with Column Sense

Award Information
Agency:
Department of Defense
Branch
Missile Defense Agency
Amount:
$49,650.00
Award Year:
1993
Program:
SBIR
Phase:
Phase I
Contract:
n/a
Agency Tracking Number:
19591
Solicitation Year:
n/a
Solicitation Topic Code:
n/a
Solicitation Number:
n/a
Small Business Information
Hypres, Inc.
175 Clearbrook Road, Elmsford, NY, 10523
Hubzone Owned:
N
Socially and Economically Disadvantaged:
N
Woman Owned:
N
Duns:
n/a
Principal Investigator:
Perng-fei Yuh, Phd
(914) 592-1190
Business Contact:
() -
Research Institution:
n/a
Abstract
A NEW CLASS OF SUPERCONDUCTING MEMORIES WITH A COLUMN-SENSE TECHNIQUE IS PROPOSED TO MAKE VERY DENSE MEMORY POSSIBLE. ALL THE EXISTING JOSEPHSON MEMORY CELLS USE ONE SENSE GATE PER CELL. AS A CONSEQUENCE, THE CELLS ARE COMPLICATED, AND THE CELL SIZE IS NOT READILY SHRUNK. THE PROPOSED SENSING SCHEME USES ONE SENSE GATE TO SENSE A GROUP (USUALLY A COLUMN) OF MEMORY CELLS, AND THEREFORE, THE CELL CAN BE SIMPLIFIED WITH THE SMALLEST POSSIBLE AREA. THIS IDEA IS VERY GENERAL, NOT LIMITED TO A PARTICULAR MEMORY CELL DESIGN. IN ADDITION, THE MEMORY CELLS ARE COMPATIBLE WITH THE NEW HIGH TEMPERATURE SUPERCONDUCTOR MATERIALS SINCE LATCHING SENSE GATES ARE NOT NECESSARY. TO ILLUSTRATE THIS IDEA, WE SHOW THAT THE 3-SQUID MEMORY CELL USED IN OUR 2-Kb MEMORY CHIP CAN BE SIMPLIFIED TO A 1-SQUID CELL WITH ONE SENSE GATE PER 256 CELLS. THE FUJITSU'S 2-JJ CAPACITIVELY COUPLED MEMORY CELL CAN ALSO BE SHRUNK TO A 1-JJ CELL WITHOUT A CAPACITOR. A FACTOR OF 2 TO 10 REDUCTION IN CELL SIZE CAN BE READILY ACHEIVED USING THE SAME DESIGN RULES. IN PHASE I, WE WILL DEMONSTRATE THE FEASIBILITY OF COLUMN SENSE IN Nb TECHNOLOGY. IN PHASE II, A SUPERCONDUCTING CACHE CHIP OF 4 TO 16 Kb WILL BE BUILT. THE IMPLEMENTATION OF A MEMORY CHIP IN NbN TECHNOLOGY OPERATING AT 10K WILL ALSO BE PURSUED IN PHASE II WITH A POTENTIAL FOR OPERATING YBCO MEMORY AT 30-40K. THE MEMORY DENSITY, CYCLE TIME, AS WELL AS DESIGN FOR TESTABILITY ARE EMPHASIZED. IN PHASE III, THE FABRICATED MEMORY CIRCUIT WILL BE INTEGRATED WITH A HYPRES SUPERCONDUCTING IR DETECTOR ARRAY AND/OR A SUPERCONDUCTING SIGNAL PROCESSING UNIT.

* information listed above is at the time of submission.

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