Multi-GHz Superconducting Logic for Digital Signal Processing and Applications for Electronic Warfare systems

Award Information
Agency: Department of Defense
Branch: Air Force
Contract: N/A
Agency Tracking Number: 20136
Amount: $98,866.00
Phase: Phase I
Program: SBIR
Awards Year: 1993
Solicitation Year: N/A
Solicitation Topic Code: N/A
Solicitation Number: N/A
Small Business Information
175 Clearbrook Road, Elmsford, NY, 10523
HUBZone Owned: N
Woman Owned: N
Socially and Economically Disadvantaged: N
Principal Investigator
 Dr. Oleg Mukhanov
 (914) 592-1190
Business Contact
Phone: () -
Research Institution
Current Electronic Warfare (EW) systems are limited to digital processing at a baseband of typically less than 100MHz, restricted by 500MS/s Analog to Digital Convertors (ADC) and l00MS/s Digital Signal Processors. HYPRES proposes to develop the key components to allow the implementation of a digital EW system with a l0GHz instantaneous bandwidth baseband. This design would replace the analog components, except for an optional first level of downconversion, with an all digital system. HYPRES has demonstrated the key elements required for a digital EW system, the operation of an 8-bit 20GS/s ADC capable of digitizing 1-18GHz input signals and superconducting logic capable of pipelined arithmetic functions at clock rates in excess of 20GHz. Several EW system architecture's have been analyzed, and their analog architecture's have been translated to a digital implementation. The advantages of digital processing are significant; processing of an 10GHz instantaneous bandwidth for interception of spread spectrum and ultra-wideband signals, signal to noise ratio does not degrade through consecutive signal processing of the signal data stream, and SNR can be enhanced by rejection of out-of-band noise. This allows for post acquisition trade-off of bandwidth for resolution. HYPRES proposes in Phase I to design, fabricate and test the key digital element required by DSP algorithms, the multiplier accumulator (MAC). Using a serial design, a multiply accumulate requires only 33 Carry Save Adders, internally operating at 33GHz, that perform the multiply accumlate operation at l GHz. Phase II will develop a complete real-time spectrum channelizer suitable for insertion into an AN/ALR-56M from LORAL. The design consists of an 8-bit ADC operating at 1GS/s and a parallel 16-pt complex FET operating at 500MS/s.

* Information listed above is at the time of submission. *

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