Subnanosecond Ultra-Low Power Consumption 3-Dimensional NbN RAM

Award Information
Agency:
Department of Defense
Branch
Missile Defense Agency
Amount:
$59,945.00
Award Year:
1997
Program:
SBIR
Phase:
Phase I
Contract:
n/a
Award Id:
35820
Agency Tracking Number:
35820
Solicitation Year:
n/a
Solicitation Topic Code:
n/a
Solicitation Number:
n/a
Small Business Information
500 Executive Boulevard, Elmsford, NY, 10523
Hubzone Owned:
N
Minority Owned:
N
Woman Owned:
N
Duns:
n/a
Principal Investigator:
Alex F. Kirichenko
(919) 592-1190
Business Contact:
() -
Research Institution:
n/a
Abstract
Due to a number of physical restrictions, Random Access Memory based on silicon can not reach the performance level of superconductive devices. HYPRES proposes the two-phase development of a subnanosecond low-power memory. The principal problems in the development of such a memory have been: an exclusive focus on ac-driven latching logic, which requires very high value of AC control currents and comparatively high power dissipation level. Recent development of the Rapid Single-Flux-Quantum (RSFQ) logic circuits have allowed a new approach to implementation of some critical components of the memory chips. This results in extremely low power dissipation (- 10 20 J per gate). The proposed memory is nonvolatile, that is data is not destroyed when the power supply is turned off. This property allows one to design a three-dimensional memory matrix. HYPRES is going to demonstrate multi-chip stacked 16 KBit three-dimensional subnanosecond access time multi-chip RAM working at 10 K temperature. The proposed above Random Access Memory can be implemented in Josephson digital electronics with focal array planes, digital signal processing, image processing, etc., as a storage of data with quick access.

* information listed above is at the time of submission.

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