Subnanosecond Ultra-Low Power Consumption 3-Dimensional NbN RAM

Award Information
Agency: Department of Defense
Branch: Missile Defense Agency
Contract: N/A
Agency Tracking Number: 35820
Amount: $59,945.00
Phase: Phase I
Program: SBIR
Awards Year: 1997
Solicitation Year: N/A
Solicitation Topic Code: N/A
Solicitation Number: N/A
Small Business Information
500 Executive Boulevard, Elmsford, NY, 10523
DUNS: N/A
HUBZone Owned: N
Woman Owned: N
Socially and Economically Disadvantaged: N
Principal Investigator
 Alex F. Kirichenko
 (919) 592-1190
Business Contact
Phone: () -
Research Institution
N/A
Abstract
Due to a number of physical restrictions, Random Access Memory based on silicon can not reach the performance level of superconductive devices. HYPRES proposes the two-phase development of a subnanosecond low-power memory. The principal problems in the development of such a memory have been: an exclusive focus on ac-driven latching logic, which requires very high value of AC control currents and comparatively high power dissipation level. Recent development of the Rapid Single-Flux-Quantum (RSFQ) logic circuits have allowed a new approach to implementation of some critical components of the memory chips. This results in extremely low power dissipation (- 10 20 J per gate). The proposed memory is nonvolatile, that is data is not destroyed when the power supply is turned off. This property allows one to design a three-dimensional memory matrix. HYPRES is going to demonstrate multi-chip stacked 16 KBit three-dimensional subnanosecond access time multi-chip RAM working at 10 K temperature. The proposed above Random Access Memory can be implemented in Josephson digital electronics with focal array planes, digital signal processing, image processing, etc., as a storage of data with quick access.

* Information listed above is at the time of submission. *

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