Low Jitter On-chip Clock Technology

Award Information
Agency: Department of Defense
Branch: Army
Contract: W15P7T-07-C-E201
Agency Tracking Number: A062-099-1208
Amount: $119,777.00
Phase: Phase I
Program: SBIR
Awards Year: 2006
Solicitation Year: 2006
Solicitation Topic Code: A06-099
Solicitation Number: 2006.2
Small Business Information
175 Clearbrook Road, Elmsford, NY, 10523
DUNS: 103734869
HUBZone Owned: N
Woman Owned: N
Socially and Economically Disadvantaged: N
Principal Investigator
 Deepnarayan Gupta
 VP Research and Development
 (914) 592-1190
 gupta@hypres.com
Business Contact
 Edward Kulinski
Title: VP Finance and Administration
Phone: (914) 592-1190
Email: ekulinski@hypres.com
Research Institution
N/A
Abstract
In true Digital-RF receiver technology, the RF signal is sampled directly at the antenna and processed digitally at high speeds. This requires an ultrafast ultra-linear analog-to-digital Converter (ADC) followed by ultrafast digital signal processing (DSP). High-speed clocks, in the 20 - 120 GHz range, are required for both the ADC and the DSP. For best performance, the ADC clock must have extremely low short-term jitter, preferably 10 fs (0.01 ps) or less. HYPRES has previously demonstrated that a Long Josephson Junction (LJJ) oscillator may be used as a clock source that meets all of these requirements, and can be integrated with rapid-single-flux-quantum (RSFQ) superconductor digital circuits. HYPRES proposes to develop a parametric family of high-frequency LJJ clocks, and to fabricate and test such an on-chip clock, phase-locked to an external low-frequency reference oscillator for long-term stability. In Phase II, a programmable modular multi-rate clock will be integrated with a superconducting ADC and DSP to provide a complete, compact digital-RF receiver system for Army communications.

* Information listed above is at the time of submission. *

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