Multi-input Synchronous Digital-RF Receiver

Award Information
Agency: Department of Defense
Branch: Navy
Contract: N00039-07-C-0002
Agency Tracking Number: N071-110-1131
Amount: $99,758.00
Phase: Phase I
Program: SBIR
Awards Year: 2007
Solicitation Year: 2007
Solicitation Topic Code: N07-110
Solicitation Number: 2007.1
Small Business Information
175 Clearbrook Road, Elmsford, NY, 10523
DUNS: 103734869
HUBZone Owned: N
Woman Owned: N
Socially and Economically Disadvantaged: N
Principal Investigator
 Deepnarayan Gupta
 VP Research and Development
 (914) 592-1190
Business Contact
 Edward Kulinski
Title: VP Finance and Administration
Phone: (914) 592-1190
Research Institution
The goal of this project is to develop an all-digital receiver system, incorporating multiple synchronous analog-to-digital converters, to enable direct digital reception from an antenna array, which permits tunable digital beamforming. HYPRES has been developing superconducting digital-RF receivers for the Navy and other DoD users based on an ultrafast ADC (sampled at over 20 GHz), featuring outstanding linearity due to intrinsic quantum accuracy. This ADC design has matured over the last decade and already exhibits an impressive spur-free-dynamic range (SFDR) greater than 100 dB and 86 dB signal-to-noise ratio over 10 MHz instantaneous bandwidth. We have also demonstrated extremely low-jitter (< 10 fs) on-chip long Josephson junction clock sources in the 10-50 GHz range. In Phase I, we propose to design, fabricate, and demonstrate a two-input prototype chip integrating two such ADCs with a common clock source, and two on-chip digital decimation filters. In addition, we will develop a multi-chip module scheme for extending this design to multiple (8-16) RF inputs, and to multiple RF bands (HF, VHF, UHF, etc.). Our goal in Phase II is to deliver a set of chips along with the necessary cryogenic and room-temperature hardware for evaluation to SPAWAR System Center.

* Information listed above is at the time of submission. *

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