Low Jitter On-chip Clock Technology

Award Information
Agency:
Department of Defense
Branch
Army
Amount:
$729,905.00
Award Year:
2007
Program:
SBIR
Phase:
Phase II
Contract:
W15P7T-07-C-A001
Award Id:
77468
Agency Tracking Number:
A062-099-1208
Solicitation Year:
n/a
Solicitation Topic Code:
n/a
Solicitation Number:
n/a
Small Business Information
175 Clearbrook Road, Elmsford, NY, 10523
Hubzone Owned:
N
Minority Owned:
N
Woman Owned:
N
Duns:
103734869
Principal Investigator:
DeepnarayanGupta
VP Research and Developme
(914) 592-1190
gupta@hypres.com
Business Contact:
EdwardKulinski
VP Finance and Administra
(914) 592-1190
ekulinski@hypres.com
Research Institute:
n/a
Abstract
In true Digital-RF receiver technology, the RF signal is sampled directly at the antenna and processed digitally at high speeds. This requires an ultrafast ultra-linear analog-to-digital Converter (ADC) followed by ultrafast digital signal processing, both of which need high-speed clocks. For best performance, the ADC clock must have extremely low short-term jitter. Building on the Phase I development of a family of 30-80 GHz on-chip low-jitter lock sources, we propose to develop X-band and Ka-band digital-RF satellite communication (SATCOM) receivers with on-chip clock. These clock sources, employing resonant long Josephson junction oscillators, exhibit extremely low short-term jitter, estimated to be less than 10 fs (0.01 ps), and therefore, are ideally suited for integration with superconductor ADCs and rapid single flux quantum (RSFQ) digital technology. An integrated on-chip clock source is indispensable for the commercial viability of HYPRES' envisioned digital-RF receiver and transceiver products. The on-chip clock eliminates the most expensive part of the receiver system, an external high-frequency clock source, and significantly reduces its size, weight, and power consumption.

* information listed above is at the time of submission.

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