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Low-Energy Adiabatic Circuits for Space Applications

Award Information
Agency: Department of Defense
Branch: Air Force
Contract: FA9453-19-P-0520
Agency Tracking Number: F18B-013-0043
Amount: $150,000.00
Phase: Phase I
Program: STTR
Solicitation Topic Code: AF18B-T013
Solicitation Number: 18.B
Solicitation Year: 2018
Award Year: 2019
Award Start Date (Proposal Award Date): 2018-12-20
Award End Date (Contract End Date): 2018-12-20
Small Business Information
145 Graham Ave ASTeCC Building
Lexintgon, KY 40506
United States
DUNS: 964938455
HUBZone Owned: No
Woman Owned: No
Socially and Economically Disadvantaged: No
Principal Investigator
 Himanshu Thapliyal
 Assistant Professor
 (859) 257-1527
Business Contact
 Kevin Donohue
Phone: (859) 913-7173
Research Institution
 University of Kentucky
 Kim Carter Kim Carter
311 Main Building
Lexington, KY 40506
United States

 (859) 257-9420
 Nonprofit College or University

Adiabatic logic-based energy-conserving circuits have potential to significantly improve energy efficiency. Adiabatic circuits recycle charge stored in load capacitance resulting in lower power dissipation as compared to conventional CMOS. However, these circuits have only targeted low-frequency operations. Research is needed to develop adiabatic logic circuits for high performance applications without sacrificing the energy efficiency. Hence, the goal of this STTR proposal is to investigate and develop circuit design techniques that can enable adiabatic logic technology to work energy efficiently at high frequency. Phase I objectives include: (i) to design representative functional blocks used in logic and memory circuits using a range of conventional and adiabatic design techniques and implement them in a CMOS process, (ii) to design adiabatic logic based energy efficient multiplier-accumulator (MAC) as the benchmark circuit using the computing and memory units proposed in objective (i). Several benchmarking experiments will be performed to understand the tradeoffs between area, speed and energy efficiency of adiabatic logic circuits compared to standard CMOS. The proposed research will enable the Air Force to determine feasibility of adiabatic logic techniques to design high performing commercial processor technologies for ultra-low power, high performance, digital processing for space applications.

* Information listed above is at the time of submission. *

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