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Low Power NCL FPGA Fast Track

Award Information
Agency: Department of Defense
Branch: Air Force
Contract: FA8651-19-C-0025
Agency Tracking Number: F2-11074
Amount: $3,861,874.00
Phase: Phase II
Program: SBIR
Solicitation Topic Code: AF00-054
Solicitation Number: 04.1
Solicitation Year: 2004
Award Year: 2019
Award Start Date (Proposal Award Date): 2019-09-20
Award End Date (Contract End Date): 2021-09-20
Small Business Information
6300 Gateway Dr.
Cypress, CA 90630
United States
DUNS: 614108918
HUBZone Owned: No
Woman Owned: No
Socially and Economically Disadvantaged: No
Principal Investigator
 Fernando Rojas
 Principal Investigator
 (714) 224-4410
Business Contact
 Ruth Craig
Phone: (714) 224-4410
Research Institution

Recently, the traditional techniques for improving clocked digital logic performance (such as device scaling) has encountered significant limitations. Theseus Logic is commercializing a unique technology that facilitates system level integrated circuit design without the timing derived limitations of traditional clocked techniques. NULL Convention Logicâ„¢ - provides a new and fundamentally more expressive “languageâ€Â for the design of digital circuits and systems. At the system level, NCL provides circuits which are inherently clockless, delay insensitive, and expressionally complete. Under this SBIR, Theseus intends to design, fabricate, and test an NCL FPGA which validates the routing versus macrocell structures investigated under Phase I. Atmel is a partner in this development and the demonstration device will be based upon the Atmel AT40K FPGA. This reduces the overall program cost since the routing, I/O, and programming software has been previously developed by Atmel.

* Information listed above is at the time of submission. *

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