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Cellular Light Sensing Array With Built-In Programmable Image Processing Functions

Award Information
Agency: Department of Defense
Branch: Air Force
Contract: N/A
Agency Tracking Number: 36126
Amount: $698,820.00
Phase: Phase II
Program: SBIR
Solicitation Topic Code: N/A
Solicitation Number: N/A
Solicitation Year: N/A
Award Year: 1998
Award Start Date (Proposal Award Date): N/A
Award End Date (Contract End Date): N/A
Small Business Information
2157 University Park Dr Suite 4
Okemos, MI 48864
United States
HUBZone Owned: No
Woman Owned: No
Socially and Economically Disadvantaged: No
Principal Investigator
 Dr. Gail Erten
 (517) 349-4544
Business Contact
Phone: () -
Research Institution

This Small Business Innovation Research project will investigate the feasibility of a programmable image processor with on-chip light sensing capability The architecture of the processor is based on cellular neural networks, which can be employed to perform many types of temporal and spatial image processing tasks through programming of the cloning templates.The proposed chip contains three distinct structures: (1) a light sensing grid, (2) a cellular neural network layer, and (3) a binarization and memory plane for ease of communication with a conventional multimedia engine. The innovative integrated structure of the chip bypasses the bottleneck and computational overload that iconic operations cause. Furthermore, some circuit structures are shared between layers to save silicon area.The cellular processor can supply parallel processing ability and high speed, while post processing and symbolic operations are carried out by a conventional multi- media digital processor. This architecture provides a flexible, programmable and sophisticated platform for fast sophisticated image processing. The system consumes little power and can be scaled down for miniature and hand-held devices.Phase I study will be geared towards proof-of-concept through system simulation. A preprototype version of the chip, such as a 16 x 16 array, will be manufactured and tested as well. In addition, interfacing options with conventional digital signal processors will be assessed.

* Information listed above is at the time of submission. *

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