Integrating Prognostics in Automated Contingency Management Strategies for Advanced Aircraft Controls

Award Information
Agency: National Aeronautics and Space Administration
Branch: N/A
Contract: NNX08CD31P
Agency Tracking Number: 070012
Amount: $99,610.00
Phase: Phase I
Program: STTR
Awards Year: 2008
Solicitation Year: 2007
Solicitation Topic Code: T1.01
Solicitation Number: N/A
Small Business Information
200 Canal View Blvd., Rochester, NY, 14623-2893
DUNS: 073955507
HUBZone Owned: N
Woman Owned: N
Socially and Economically Disadvantaged: N
Principal Investigator
 Gregory Kacprzynski
 Principal Investigator
 () -
Business Contact
 Carol Marquardt
Title: Business Official
Phone: (585) 424-1990
Research Institution
 Georgia Tech Research Corporation
 Not Available
 Industry Contracting Office, 505 Tenth Street, NW
Atlanta, GA, 30318
 (404) 894-6929
 Nonprofit college or university
Impact Technologies, in collaboration with Georgia Institute of Technology, proposes to develop and demonstrate innovative technologies to integrate prognostics into Automated Contingency Management (ACM) for advanced aircraft controls. Without consideration of prognostic information, the traditional reactive fault tolerant control approaches may fail to provide optimal fault mitigation/accommodation strategies over a longer period of time. The project team will create a platform level simulation environment that demonstrates the fault propagation from the component level, using electromechanical flight actuators (EMAs) as a testbench problem, to the high level flight envelope and mission objectives. The proposed ACM system accepts input from discrete diagnostics, grayscale diagnostics and prognostic modules and will be split into a real-time reactive component and a "planning" component that considers temporal parameters and the potential impact of being proactive with mitigating action. Specifically, innovative prognostics enhanced stochastic programming and receding horizon control techniques are proposed for high and low level ACM controllers respectively. A subset of core algorithms will be implemented on embedded systems and used in hardware-in-the-loop demonstrations to justify a Technology Readiness Level of 4.

* Information listed above is at the time of submission. *

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