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Computer Architecture, Algorithms, Models and Simulations

Award Information
Agency: Department of Defense
Branch: Missile Defense Agency
Contract: N/A
Agency Tracking Number: 35775
Amount: $59,975.00
Phase: Phase I
Program: SBIR
Solicitation Topic Code: N/A
Solicitation Number: N/A
Timeline
Solicitation Year: N/A
Award Year: 1997
Award Start Date (Proposal Award Date): N/A
Award End Date (Contract End Date): N/A
Small Business Information
8130 Boone Blvd., Suite 500, Vienna, VA, 22182
DUNS: N/A
HUBZone Owned: N
Woman Owned: N
Socially and Economically Disadvantaged: N
Principal Investigator
 Mark Sullivan, Phd.
 (703) 448-1116
Business Contact
Phone: () -
Research Institution
N/A
Abstract
Reconfigurable computing architectures based on Field Programmable Gate Arrays (FPGAs) offer extaordinary real time processing rates in inexpensive programmable hardware. The key to using FPGAs for reconfigurable computing is to reformulate algorithms in terms of parallel operations that are easily implemented with chains of simple processing elements. Currently available commercial integrated circuits appear to be capable of performing about four billion arithmetic operations per second in certain digital signal processing applications. ISL has developed novel numerical algorithms that are ideally suited for implementation on FPGAs. The focus of the proposed Phase I effort is to identify design methodologies that map these algorithms into FPGA designs that fully exploit the computational resources of the FPGA. The capabilities of FPGA-based reconfigurable computing archi-tectures will then be compared to those of competing architectures using parallel systems of conventional processors.

* Information listed above is at the time of submission. *

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