Broadband Solid-State Power Amplifier Predistortion Linearization Scheme

Award Information
Agency:
Department of Defense
Amount:
$79,967.00
Program:
SBIR
Contract:
N68335-07-C-0007
Solitcitation Year:
2006
Solicitation Number:
2006.2
Branch:
Navy
Award Year:
2006
Phase:
Phase I
Agency Tracking Number:
N062-116-0529
Solicitation Topic Code:
N06-116
Small Business Information
INFORMATION SYSTEMS LABORATORIES, INC.
10070 Barnes Canyon Road, San Diego, CA, 92121
Hubzone Owned:
N
Woman Owned:
N
Socially and Economically Disadvantaged:
N
Duns:
107928806
Principal Investigator
 Pei-hwa Lo
 Principal Engineer
 (703) 448-1116
 phl@isl-inc.com
Business Contact
 Sandra Quintero
Title: Senior Contracts Administ
Phone: (858) 373-2711
Email: squintero@islinc.com
Research Institution
N/A
Abstract
Recent advancements on linearizing power amplifiers using the LINC (Linearization on Non-linear Components) architecture have attracted attentions on researchers and engineers. This is primarily caused by two reasons. (1) Maturity and availability of high density and high speed digital electronics signal processing hardware (e.g. DSP or FPGA) make complex signal decomposition computation feasible for real time operation. (2) LINC architecture offers a true uncompromising solution for both linearity and efficiency on power amplifier realization. To resolve the channel imbalance and output combiner distortions issues encountered by the LINC architecture power amplifier, an efficient adaptive digital predistortion technique is proposed. The technique continuously monitors the channel signal conditions and the amplifier output signal quality in order to properly adjust the predistortion gain and phase in the channel signals. The resulting adaptive digital predistortion LINC power amplifier provides superior linearity and efficiency with practical commercial off-the-shelf components. Simulations and analysis will be performed to quantify the performance improvements resulting from the adaptive digital predistortion technique. The proposed technique is amenable to real time implementation on the DSP (digital signal processor) and FPGA (Field programmable gate array) digital hardware.

* information listed above is at the time of submission.

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