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Next Generation Radar and Electronic Warfare Processing Technology

Award Information
Agency: Department of Defense
Branch: Navy
Contract: N68335-20-C-0974
Agency Tracking Number: N202-095-0399
Amount: $139,837.00
Phase: Phase I
Program: SBIR
Solicitation Topic Code: N202-095
Solicitation Number: 20.2
Timeline
Solicitation Year: 2020
Award Year: 2020
Award Start Date (Proposal Award Date): 2020-09-16
Award End Date (Contract End Date): 2021-03-22
Small Business Information
2904 Westcorp Blvd Suite 210
Huntsville, AL 35805-1111
United States
DUNS: 832864370
HUBZone Owned: Yes
Woman Owned: No
Socially and Economically Disadvantaged: No
Principal Investigator
 Cameron Musgrove
 (256) 319-2026
 cameron.musgrove@ierustech.com
Business Contact
 Zac Snodgrass
Title: zac_snodgrass
Phone: (256) 503-5019
Email: zac.snodgrass@ierustech.com
Research Institution
N/A
Abstract

IERUS Technologies proposes to develop and demonstrate a methodology for evaluating synthetic aperture radar (SAR) and airborne electronic attack (AEA) hardware processing technology options. Technology and processing capabilities continue to change at a rapid pace. As the drivers for processing capability may change from gamers of a decade ago to today’s machine learning needs, there is a need for niche applications like radar processing to take advantage of these innovations. Whether or not radar processing may be unique to the current technology drivers, the longevity of the capability requires an ongoing evaluation of technology to measure its value for radar processing. Compounding the difficulty in comparing performance between hardware architectures is that the implementation of the algorithm must be tailored for each application. For example, GPU processing power measures in the TFLOPS, but this drops as the floating-point number precision increases; the complex valued, high dynamic range of SAR imagery requires precision that may result in performance less than advertised. While FPGAs have impressive resources, their processing capability depends precisely upon the particular chip, algorithm, access to memory, and design implementation.  For radar systems with low-volume of production of units, it is desirable to use COTS hardware to ride the wave of technological innovation and take advantage of cost savings of the marketplace. Non-recurring engineering costs (NRE) can be substantial to design, fabricate, integrate, and test a new processor every 12-18 months as new processing modules become available. General purpose workstation class computers are extremely cost-efficient in terms of raw processing power, memory, and data storage. However, these systems can be extremely large and power inefficient.  The focus of the phase 1 effort will be to develop a method to measure hardware processing performance specific to SAR, validate that method with a cost-effective and high-performance platform, and estimate processing hardware to scale the solution for a specific data throughput requirement.

* Information listed above is at the time of submission. *

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