Next Generation Reconfigurable Field Programmable Gate Array

Award Information
Agency: Department of Defense
Branch: Air Force
Contract: FA9453-09-M-0069
Agency Tracking Number: F083-187-0125
Amount: $100,000.00
Phase: Phase I
Program: SBIR
Awards Year: 2009
Solicitation Year: 2008
Solicitation Topic Code: AF083-187
Solicitation Number: 2008.3
Small Business Information
Analytic Design Laboratories
3750 W 1975 N, Plain City, UT, 84404
DUNS: 140996674
HUBZone Owned: N
Woman Owned: N
Socially and Economically Disadvantaged: N
Principal Investigator
 John Campbell
 President
 (801) 825-7716
 ckuznia@ultracomm-inc.com
Business Contact
 John Campbell
Title: President
Phone: (801) 825-7716
Email: ckuznia@ultracomm-inc.com
Research Institution
N/A
Abstract
Analytic Design Laboratories proposes a Next Generation FPGA that is deterministically place and routable.  Conventional FPGAs rely on synthetic annealing to optimize function placement and connection routing.  Synthetic annealing randomly moves functions and connecting paths to improve circuit performance to an acceptable level.  The side effect of random improvement is jumbled signal flow and greater need for connectivity.  Deterministic placement and routing preserves orderly flow of information across the chip and allows chip real estate otherwise used for connectivity to be redirected to providing additional computational resources.  Orderly flow of data is a characteristic of machinery built from programs written in high-level computer languages and the Next Generation FPGA, by enabling deterministic routing, makes greater computational resources available to the software. BENEFIT: Being able to deterministically place and route an FPGA results in more computational power being concentrated within the Next Generation FPGA for use in executing software.  Deterministic routing has the additional benefit of being much faster than synthetic annealing, something that aids the system developers.  The algorithm enabling deterministic place and route also enables automatic allocation of software codes to the optimal chip in a system consisting of Next Generation FPGAs, conventional FPGAs, and microprocessors.

* information listed above is at the time of submission.

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