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Develop integrated analog photonic modulator components compatible with photonic foundry production

Award Information
Agency: Department of Defense
Branch: Air Force
Contract: FA8650-18-C-1734
Agency Tracking Number: F171-126-0341
Amount: $749,334.00
Phase: Phase II
Program: SBIR
Solicitation Topic Code: AF171-126
Solicitation Number: 17.1
Timeline
Solicitation Year: 2017
Award Year: 2018
Award Start Date (Proposal Award Date): 2018-09-14
Award End Date (Contract End Date): 2020-09-14
Small Business Information
51 East Main Street Suite 201
Newark, DE 19711
United States
DUNS: 805473951
HUBZone Owned: No
Woman Owned: No
Socially and Economically Disadvantaged: No
Principal Investigator
 Peng Yao
 Principal Investigator
 (302) 456-9003
 yao@phasesensitiveinc.com
Business Contact
 Ahmed Sharkawy
Phone: (302) 286-5191
Email: Sharkawy@phasesensitiveinc.com
Research Institution
N/A
Abstract

In phase II work, we will collaborate with Prof. Dennis W. Prather in UD and continue to develop broadband, low VÏ€, high linearity, thin-film lithium niobate on insulator (LNOI) modulators that are fully compatible with silicon photonic integrated circuits (PIC) foundry processes. We will demonstrate a low VÏ€, broadband, small footprint LNOI modulator with hybrid Si/LN or SiN/LN waveguide using the proposed integration process. We will study different coupling schematics for characterization and further system integration of the hybrid LNOI modulator. We will explore and develop linearized modulators using novel linearization techniques. We will develop and refine the critical wafer bonding and thin-film transferring processes using our new wafer bonding tool to improve fabrication reliability and uniformity. PSI will also start working on a PIC solution to our analog feed network for Tx phased arrays. We will condense many of the current functionalities into a single PIC chip design using available building elements as well as new devices modified based on the AIM photonics PDK tool box. We are planning to optimize the design and prepare for tape-outs to test the developed devices, subsystems and a full Tx processor chip.

* Information listed above is at the time of submission. *

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