VHSIC DESIGN FOR COMPUTING THE DISCRETE FOURIER TRANSFORM USING RESIDUE FERMAT NUMBER SYSTEM

Award Information
Agency:
Department of Defense
Branch
Navy
Amount:
$496,000.00
Award Year:
1986
Program:
SBIR
Phase:
Phase II
Contract:
n/a
Award Id:
2300
Agency Tracking Number:
2300
Solicitation Year:
n/a
Solicitation Topic Code:
n/a
Solicitation Number:
n/a
Small Business Information
2442 33rd St, Santa Monica, CA, 90405
Hubzone Owned:
N
Minority Owned:
N
Woman Owned:
N
Duns:
n/a
Principal Investigator:
Trieu-kien Truong
(213) 398-2785
Business Contact:
() -
Research Institution:
n/a
Abstract
THE DEVELOPMENT OF VHSIC DEVICES PRESENTS MANY NEW AND CHALLENGING AREAS OF RESEARCH. BY USING THE RESIDUE FERMAT NUMBER SYSTEM TO IMPLEMENT A VHSIC DISCRETE FOURIER TRANSORM (DFT) IN CMOS CHIP, REQUIRED ONLY A SMALL NUMBER OF MULTIPLICATIONS. THE TRADITIONAL DFT DESIGN REQUIRED VERY LARGE NUMBER OF MULTIPLICATIONS, VERY COMPLICATED CIRCUIT, AND LARGE AREAS. THE PROPOSED NEW DESIGN DFT WOULD -RESULT IN A VERY COMPACT VLSI CHIP, VERY HIGH PERFORMANCE, AND VERY LOW POWER CONSUMPTION. THE OBJECTIVE OF THIS PROPOSAL IS TO DESIGN, DEVELOP, AND IMPLEMENT A STATE-OF-THE-ART DFT CHIP FOR ANY APPLICATIONS RELATED TO DIGITAL SIGNAL PROCESSING. THE FIRST PHASE OF THIS PROPOSAL, ATTENTION IS FOCUSED ON THE THEORETICAL BACKGROUND OF USING RESIDUE FERMAT NUMBER SYSTEM TO IMPLEMENT A DFT, AND THEN FOCUSED ON THE POSSIBLE CONFIGURATION OF LOGIC STRUCTURES. THE PHYSICAL IMPLEMENTATION OF THE DFT WILL BE A 16-POINT DFT.

* information listed above is at the time of submission.

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