You are here

Reconfigurable VLIW Processor for Software Defined Radio

Award Information
Agency: National Aeronautics and Space Administration
Branch: N/A
Contract: NNX10CC60P
Agency Tracking Number: 095618
Amount: $100,000.00
Phase: Phase I
Program: SBIR
Solicitation Topic Code: O1
Solicitation Number: N/A
Timeline
Solicitation Year: N/A
Award Year: 2010
Award Start Date (Proposal Award Date): N/A
Award End Date (Contract End Date): N/A
Small Business Information
2705 W Byron St, Chicago, IL, 60618
DUNS: 361627933
HUBZone Owned: N
Woman Owned: N
Socially and Economically Disadvantaged: N
Principal Investigator
 Miroslav Velev
 Principal Investigator
 (773) 856-6633
 miroslav.velev@aries-da.com
Business Contact
 Miroslav Velev
Title: Business Official
Phone: (773) 856-6633
Email: miroslav.velev@aries-da.com
Research Institution
N/A
Abstract
We will design and formally verify a VLIW processor that is radiation-hardened, and where the VLIW instructions consist of predicated RISC instructions from the PowerPC 750 Instruction Set Architecture (ISA). The PowerPC 750 ISA is used in the radiation-hardened RAD750 flight-control computer that is utilized in many NASA space missions, including Deep Impact, the Mars Reconnaissance Orbiter, the Mars Rovers, and is planned to be used in the Crew Exploration Vehicle (CEV). The VLIW processor will have reconfigurable functional units and specialized instructions that will be optimized for Software Defined Radio applications. The radiation-hardening will be done at the microarchitectural level with a mechanism that will allow the detection and correction of all timing errors---caused not only by radiation, but also by variations in the voltage, frequency, manufacturing process, and aging of the chip. The binary-code compatibility of the resulting VLIW processors with the PowerPC 750 ISA will allow them to seamlessly execute legacy binary code from previous space missions. We have made critical contributions to the fields of formal verification of complex pipelined microprocessors, and Boolean Satisfiability (SAT), and have developed highly efficient Electronic Design Automation (EDA) tools that we will use.

* Information listed above is at the time of submission. *

US Flag An Official Website of the United States Government