AUTOMATICALLY RETARGETABLE ADA AND C COMPILERS FOR MULTI-PROCESSOR NETWORKS

Award Information
Agency: Department of Defense
Branch: Navy
Contract: N/A
Agency Tracking Number: 20401
Amount: $50,175.00
Phase: Phase I
Program: SBIR
Awards Year: 1993
Solicitation Year: N/A
Solicitation Topic Code: N/A
Solicitation Number: N/A
Small Business Information
1036 West Taft Avenue, Orange, CA, 92665
DUNS: N/A
HUBZone Owned: N
Woman Owned: N
Socially and Economically Disadvantaged: N
Principal Investigator
 Robert J. Sheraga
 (714) 974-2201
Business Contact
Phone: () -
Research Institution
N/A
Abstract
JRS is proposing to provide a software tool that will demonstrate efficient mapping of Ada and ANSI Standard "C" onto Uni-processor architecture, based on VHDL models of the target architecture. This demonstration will utilize the JRS IDAS tool set, which has been effectively applied to this problem, for several very high performance signal processing systems, over the past few years. JRS is also proposing to perform a design study and to define an approach for extending the Uni-processor capability, demonstrated above, to a multi-processor (i.e., network) capability. The approach will be based on the Navy PGM toolset and the capabilities of Ada 9X. The study will be performed around a general Attached Processor System Model that was developed in an earlier study for NAVSEA. This model has been found by JRS to be applicable to most modern military signal and image processing systems. In Phase II, the multi-processor capability will be implemented within the IDAS framework and the resulting prototype will be demonstrated on a Navy provided algorithmic processing chain.

* Information listed above is at the time of submission. *

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