Just in Time Ontology Mapping for Manufacturing System Integration

Award Information
Agency: Department of Commerce
Branch: N/A
Contract: SB1341-02-W-1022
Agency Tracking Number: 7.11.05
Amount: $74,927.00
Phase: Phase I
Program: SBIR
Awards Year: 2002
Solicitation Year: N/A
Solicitation Topic Code: N/A
Solicitation Number: N/A
Small Business Information
1215 17th Street N.W., Suite 101, Washington, DC, 20036
DUNS: 944819697
HUBZone Owned: N
Woman Owned: N
Socially and Economically Disadvantaged: N
Principal Investigator
 Sidney Bailin
 (202) 467-9588
Business Contact
 Sidney Bailin
Title: President
Phone: () -
Email: sbailin@kevol.com
Research Institution
Large-scale manufacturing system interoperability requires the interchange of both process and product specifications. The heterogeneity of process representations makes this difficult. NIST's Manufacturing Systems Integration Division has developed the Process Specification Language (PSL) as a means of overcoming these problems. PSL is intended to serve as an inter-lingua, a common representation that can be used to mediate between application-specific or ontologies. A fundamental part of the PSL vision is a collection of translators between PSL and these other ontologies. The challenge is to develop such translators in a manner that is both cost-effective and adequate to the needs of client applications. Our intention is to apply just-in-time (JIT) techniques to this challenge. JIT ontology mapping is a dynamic approach in which only those parts of an ontology that are needed in a given application context are translated. The research conjecture is that JIT can greatly facilitate the implementation, deployment, and maintenance of PSL extensions and translators.

* Information listed above is at the time of submission. *

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