Deep Learning Processing Subsystem (DLPS): A HPSC-Compatible Deep Learning Coprocessor

In this proposed effort, we propose to develop a Deep Learning Processing Subsystem (DLPS) solution for HPSC system. The DLPS solution can significantly improve the performance and energy efficiency of the HPSC system in processing deep learning algorithms. The key innovations of this proposal include design and development of an low-power and high- performance deep learning processing system, they are: (1) low-power and high- performance DLPS hardware; (2) a HPSC-compatible software module to manage DLPS hardware and provide API to application layer; (3) a DLPS toolchain to transform deep learning models from popular frameworks such as Keras, TensorFlow, and Caffe; (4) DLPS hardware implementation on space-grade Xilinx FPGA platform for fault-tolerance design. Finally, all the proposed techniques will be integrated in a functional prototype system to demonstrate the capabilities, performances, and interoperability of proposed architecture