SBIR Phase I: Design of a 10-Gigabit Ethernet Transceiver Over Copper

Award Information
Agency: National Science Foundation
Branch: N/A
Contract: 0441632
Agency Tracking Number: 0441632
Amount: $100,000.00
Phase: Phase I
Program: SBIR
Awards Year: 2005
Solicitation Year: N/A
Solicitation Topic Code: N/A
Solicitation Number: N/A
Small Business Information
6600 Fountain Lane North, Maple Grove, MN, 55311
HUBZone Owned: N
Woman Owned: N
Socially and Economically Disadvantaged: N
Principal Investigator
 Yongru Gu
 (612) 220-4647
Business Contact
 Keshab Parhi
Phone: (612) 220-4647
Research Institution
This Phase I Small Business Innovation Research (SBIR) project will address the tradeoffs involved in design and implementation of a 10-gigabit ethernet transceiver over unshielded twisted pair (UTP) copper cables of category 6 or 7. The IEEE standards committee 802.3-an was created in Feb. 2004 to study and create a new standard for this purpose. Design and implementation of these tranceivers at 10 Gbps have never been demonstrated. The receiver design is challenging not only with respect to algorithm considerations for equalization and decoding and noise cancellations but also with respect to hardware implementations at 10 Gbps. The former requires extensive simulations of receiver algorithms and performance tradeoff analysis while the latter requires extensive architectural considerations with respect to feasibility of speed and power consumption. The cost and power are primary constraints. Current Gigabit transceivers consume about 1 Watt power. In order for the 10-Gigabit transceivers to be attractive, they will need to consume less than 8 Watts. This phase I study will expand and attempt to commercialize the current and prior efforts of the PI. It will address both transmitter-receiver design and architecture design for VLSI integrated chip implementation. The tradeoffs of various modulation schemes and coding schemes will be studied. The results of these studies will be presented to the standards committee and will be published at various conferences. The architecture design issues will address 10-gigabit implementation of complex blocks such as LDPC decoder, LDPC encoder, Tomlinson-Harashima Precoder (THP), and other echo and next cancellers. Parallel decision feedback equalizers and decoders operating at 10 Gbps will be studied. The demonstration of this system will allow companies such as Cisco, Force-10 and Avaya to include this as part of their 10-gigabit systems. The business opportunities for 10-gigabit ethernet transceivers are many! The chips will revolunize data transmission in data centers now and desktops in a few years. The technology generated through this study will be of interest to other ethernet systems such as 2.5 or 5 Gbps over low-grade low-cost existing copper cables of type category-5 and 5e. The broader impacts of this research can be felt by having data available at 10 Gbps at desktops everywhere in a few years. This is an order of magnitude higher speed than what is possible to achieve today. Other impacts include dramatic cost reduction by using copper instead of fiber, longer distance reach by using sophisticated signal processing algorithms and architectures in the transmitter and receiver.

* Information listed above is at the time of submission. *

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