Techniques and Processes for Rendering Mobile Technology Forensically Irrecoverable

Award Information
Agency:
Department of Defense
Branch
Office of the Secretary of Defense
Amount:
$374,991.00
Award Year:
2007
Program:
SBIR
Phase:
Phase II
Contract:
N00178-07-N-1043
Award Id:
78656
Agency Tracking Number:
O053-A07-4110
Solicitation Year:
n/a
Solicitation Topic Code:
n/a
Solicitation Number:
n/a
Small Business Information
P. O. 624, 534 Lawrence Street, Moulton, AL, 35650
Hubzone Owned:
N
Minority Owned:
N
Woman Owned:
N
Duns:
794777847
Principal Investigator:
JamesLewis
Chief Technical Officer
(256) 905-0775
james.lewis@lewisinnovative.com
Business Contact:
ElizabethLewis
President
(256) 905-0775
elizabeth.lewis@lewisinnovative.com
Research Institute:
n/a
Abstract
LIT will improve FPGA sanitization techniques, develop Tamper Detection (TD) technology, and begin developing an Anti-Tamper Integrated Circuit (AT IC). LIT will pursue National Security Agency (NSA) qualification of the developed products and technology as appropriate. In Phase I LIT developed techniques for sanitizing FPGAs and associated configuration memory. In Phase II LIT will develop improvements to FPGA Sanitization in the areas of: 1. Sanitization Verification of FPGA Internal Structures 2. Incorporating NSA Approved FLASH Device Sanitization 3. Improvement of Sanitization Speed LIT will develop an Anti-Tamper Integrated Circuit (AT IC) that incorporates FPGA sanitization technology and other AT features. The LIT AT IC will be Multi-Chip Module (MCM) that includes an FPGA, configuration memory, and structures designed to eliminate access to configuration bit stream data and to provide robust Anti-Tamper and Tamper Detection capabilities. In Phase II LIT will build PCB prototypes of the AT IC. In Phase I LIT developed continuous authentication techniques that ensure that devices are operating in their intended environment. In Phase II, in connection with development of the AT IC, LIT will expand Tamper Detect (TD) techniques to allow detection of removal of a single IC from a PCB.

* information listed above is at the time of submission.

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