VLSI HIGH THROUGHPUT RATE ARCHITECTURES FOR SYSTOLIC ARRAY PROCESSORS

Award Information
Agency:
National Science Foundation
Branch
n/a
Amount:
$199,582.00
Award Year:
1990
Program:
SBIR
Phase:
Phase II
Contract:
n/a
Award Id:
10690
Agency Tracking Number:
10690
Solicitation Year:
n/a
Solicitation Topic Code:
n/a
Solicitation Number:
n/a
Small Business Information
710 Silver Spur Rd #285, Rolling Hills Est, CA, 90274
Hubzone Owned:
N
Minority Owned:
N
Woman Owned:
N
Duns:
n/a
Principal Investigator:
Tsun-yee Yan
Principal Investigator
(213) 373-3384
Business Contact:
() -
Research Institution:
n/a
Abstract
THE LEAST-SQUARES (I.S.) ALGORITHM IS THE BASIS FOR MANY MODERN SIGNAL PROCESSING APPLICATIONS INCLUDING SPECTRAL ANALYSIS, BEAM FORMATION, DIRECTION FINDING, ADAPTIVE ANTENNA ARRAY, EQUALIZATION, KALMAN FILTERING AND PARAMETER ESTIMATION. TRIANGULAR AND LINEAR SYSTOLIC ARRAYS ARE THE MOST EFFICIENT WAYS TO ACHIEVE HIGH COMPUTATIONAL THROUGHPUTRATES FOR HIGH PERFORMANCE REAL-TIME APPLICATIONS. THE RESEARCHERS PROPOSE A DETAILED COMPARISON OF THE ARITHMETICAL COMPLEXITY (NUMBER OF MULTIPLES, DIVIDES, ETC.)AND FINITE PRECISION COMPUTATIONAL EFFECTS OF THE TRIANGULARAND LINEAR INTERNAL AND BOUNDARY SYSTOLIC PROCESSING CELLS UNDER GIVENS, FAST GIVENS, MODIFIED FAST GIVENS, MODIFIED GRAM-SCHMIDT, AND HOUSEHOLDER TRANSFORMATIONS FOR I.S. ESTIMATION BASED ON THE QR DECOMPOSITION APPROACH. BY SELECTING THE PROCESSING ALGORITHM WITH THE LEAST COMPUTATIONAL COMPLEXITY, THEY CAN DETERMINE THE ARCHITECTURE OF THE HIGH THROUGHPUT RATE SYSTOLIC ARRAY PROCESSOR FOR VLSI FABRICATION. A GENERIC (PROGRAMMABLE) SYSTOLIC ARRAY PROCESSING CHIP CAN BE DEVELOPED FOR A VARIETY OF SIGNAL PROCESSING APPLICATIONS.

* information listed above is at the time of submission.

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