SBIR Phase I: TriStar, An Algebraic High Performance Communications Signal Processor
National Science Foundation
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Small Business Information
The Athena Group, Inc.
408 West University Avenue, Suite 306, GAINESVILLE, FL, 32601
Socially and Economically Disadvantaged:
AbstractThis Small Business Innovation Research (SBIR) Phase I project will research and develop an innovative and revolutionary core wireless infrastructure technology. Wireless technologies impact virtually every aspect of life and require a new high performance, low latency, low power infrastructure technology to move to the next level. Today, communications and digital signal processors (DSPs) achieve high performance levels by creating multi-processor designs; as a consequence, these systems can be overly complex, costly, and power consuming. The proposed project utilizes a high-performance communications and DSP processor design; one based on an understanding of computer arithmetic rather than a massive infusion of hardware. The Phase I project will (1) develop a mathematical framework in which physically realizable multiplier-less TriStar filters and transforms having user defined critical frequency or frequencies can be derived, (2) develop a design methodology that can optimize TriStar solutions for speed, power, complexity and/or latency; and (3) quantify and validate the performance and packaging gains using powerful EDA tools. The hardware implementation of the resulting multiplier-free system will achieve superior performance, cost, and power consumption when compared to today?s best wireless solutions. The broader impact/commercial potential of this project is found in the rapidly increasing $200B (US) wireless market, a market with rapidly increasing technological demands and requirements. The proposed technology represents a major advance in the foundation or infrastructure technology that underlies a wide range of communications, sensor, instrumentation, and telemetry applications. It brings multiple efficiencies to these applications, delivering improved performance, reduced power, reduced silicon area and silicon expense, and run-time reconfigurability. The proposed technology delivers these basic economic justifications while simultaneously delivering such game-changing benefits as extended product life cycle, and improved product performance which can be expressed in attributes consumers prize: longer battery life and faster wireless data rates. Commercial product release will be in a form preferred by the targeted customer-base, namely as semiconductor intellectual property (IP) cores ready for use in semiconductor chip manufacturing. As a result, customers can rapidly and affordably develop and evaluate new wireless solutions and scientific instruments that provide their customers and the public with more affordable, capable, and reliable wireless systems, devices, and accessories.
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