System Engineer Toolset for Fault Tolerant Design

Award Information
Agency:
Department of Defense
Branch
Defense Advanced Research Projects Agency
Amount:
$98,902.00
Award Year:
1996
Program:
SBIR
Phase:
Phase I
Contract:
n/a
Agency Tracking Number:
32513
Solicitation Year:
n/a
Solicitation Topic Code:
n/a
Solicitation Number:
n/a
Small Business Information
Management Sciences, Inc.
6022 Constitution Ave. N.E., Albuquerque, NM, 87110
Hubzone Owned:
N
Minority Owned:
N
Woman Owned:
N
Duns:
n/a
Principal Investigator:
Kenneth Blemel
(505) 255-8611
Business Contact:
() -
Research Institution:
n/a
Abstract
This SBIR will explore and develop new automated methods for dynamic fault tolerance in defense electronic systems. The research will investigate using the software of digital signal processor operating systems to pro-actively map defective operations to remaining processors. In the past, fault tolerance has relied on passive redundancy to extend operating life. With software, a simple re-start, or a shift to non-corrupted memory and processor may be all that is needed. In Phase I, research will be based in ongoing Rapid Prototyping of Application Specific Signal Processors (RASSP) development. The RASSP design tools and project scientists will be used to develop the algorithms that provide scalable, heterogeneous computing systems with a new breed of fault tolerance based on dynamic reconfiguration of resources. In Phase II the system will be developed using networked UNIX computers. In Phase II the technology will be tried aboard a US Navy combat ship.

* information listed above is at the time of submission.

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