You are here

Heterogeneous computing system with dynamic fault tolerance to radiation harden commercial microelectronics (Hetero-Hard)

Award Information
Agency: Department of Defense
Branch: Missile Defense Agency
Contract: HQ0860-22-C-7080
Agency Tracking Number: B212-022-0126
Amount: $149,912.00
Phase: Phase I
Program: SBIR
Solicitation Topic Code: MDA21-022
Solicitation Number: 21.2
Solicitation Year: 2021
Award Year: 2022
Award Start Date (Proposal Award Date): 2021-12-06
Award End Date (Contract End Date): 2022-06-05
Small Business Information
6820 Moquin Dr NW
Huntsville, AL 35806-2900
United States
DUNS: 185169620
HUBZone Owned: No
Woman Owned: No
Socially and Economically Disadvantaged: No
Principal Investigator
 Karthikeyan Lingasubramanian
 (205) 529-9290
Business Contact
 Tanu Singhal
Phone: (256) 361-0799
Research Institution

In this work, we propose a heterogenous computing system which can seamlessly integrate with the commercial off the shelf (COTS) part and provide design hardening against radiation without modifying the inherent design of the COTS part. The heterogenous computing system will employ an in-situ radiation monitoring system and dynamic fault tolerant system, which will be designed using the vendor provided information of the COTS part. Also, since these systems are like add-ons and not part of the COTS part’s circuit design, the effect on inherent performance characteristics of the COTS part will be minimal. In Phase I, we will focus on the base design of proposed heterogenous computing system using a digital COTS part as circuit under test (CUT). We will work closely with University of Tennessee at Chattanooga (UTC) to design and implement tests and validations to prove the validity of the proposed system. A machine learning based intelligent mathematical model will be designed to monitor radiation effects in COTS CUT. A selective redundancy-based fault tolerance model will be designed to dynamically mitigate radiation effects. Finally, the individual modules, radiation monitor, fault tolerance, will be integrated using a heterogenous computing system that utilizes Graphic Processing Unit (GPU) and Field Programmable Gate Array (FPGA). In Phase II, we will focus on the optimization of the proposed methodology by adjusting the design to achieve desired performance. We will expand the proposed system’s capability to address an analog circuit block. Prominent analog COTS parts like analog-to-digital and digital-to-analog converters (ADC/DAC) will be used as CUT, and the proposed system and its modules will be tested and validated. The comprehensively optimized system will be fabricated and tested with physical COTS parts. Approved for Public Release | 21-MDA-11013 (19 Nov 21)

* Information listed above is at the time of submission. *

US Flag An Official Website of the United States Government