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Continuous-Time Digital Signal Processing (CTDSP) Using Reconfigurable Devices

Award Information
Agency: Department of Defense
Branch: Army
Contract: W9113M-22-C-0077
Agency Tracking Number: A2-8859
Amount: $1,097,891.20
Phase: Phase II
Program: SBIR
Solicitation Topic Code: A20-080
Solicitation Number: N/A
Solicitation Year: 2020
Award Year: 2022
Award Start Date (Proposal Award Date): 2022-04-01
Award End Date (Contract End Date): 2024-03-28
Small Business Information
2904 Westcorp Blvd Suite 210
Huntsville, AL 35805-1111
United States
DUNS: 832864370
HUBZone Owned: No
Woman Owned: No
Socially and Economically Disadvantaged: No
Principal Investigator
 Dane Phillips
 (256) 319-2026
Business Contact
 Dan Bodeker
Phone: (256) 319-2026
Research Institution

Modern missile systems require tremendous amounts of signal and information processing using constrained resources in an extreme environment.  Multi-spectral sensors, high-bandwidth communications, and supersonic flight control demand significant processing power, while space and weight constraints limit available power and heat dissipation. It is uncertain that conventional Digital Signal Processing (DSP) approaches can provide the increased performance required in next generation missile systems.  To meet this need, alternatives to conventional, power-hungry digital processing approaches are desired. The effort proposed here continues the investigations and implementation  of a promising novel approach in continuous-time digital signal processing (CTDSP), which achieves similar or improved performance while potentially offering a significant decrease in power and heat dissipation requirements.  These algorithms have been implemented on reconfigurable hardware, field programmable gate arrays (FPGAs) to enable the flexible design of future systems.  During the phase II effort, the development team will advance the Phase I results by refining the developed CTDSP blocks and design methodologies in order to create robust architectures to operate across an abundance of FPGAs and application scenarios. Throughout this refinement, the team will continue to develop practical implementation and parameter recommendations that fall for flexible integration based on user needs.

* Information listed above is at the time of submission. *

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