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Innovating Cryo-CMOS PDKs and ICs

Award Information
Agency: Department of Defense
Branch: Army
Contract: W911NF-22-C-0039
Agency Tracking Number: A2-9068
Amount: $1,149,650.34
Phase: Phase II
Program: STTR
Solicitation Topic Code: A20B-T005
Solicitation Number: 20.B
Timeline
Solicitation Year: 2020
Award Year: 2022
Award Start Date (Proposal Award Date): 2022-04-14
Award End Date (Contract End Date): 2024-04-30
Small Business Information
5847-A UPLANDER WAY
CULVER CITY, CA 90230-1111
United States
DUNS: 079394442
HUBZone Owned: No
Woman Owned: No
Socially and Economically Disadvantaged: No
Principal Investigator
 Philbert Marsh
 (310) 429-6271
 phil@carbonicsinc.com
Business Contact
 Kosmas Galatsis
Phone: (310) 874-3024
Email: kos@carbonicsinc.com
Research Institution
 Georgia Institute of Technology
 Arijit Raychowdhury
 
North Avenue
Atlanta, GA 30332-0001
United States

 (404) 894-1789
 Nonprofit College or University
Abstract

Within this Phase-II STTR program, Carbonics and Georgia Tech will develop cryogenic CMOS devices and circuits and support them with compact models valid from 4.2K to over 300K to enable applications such as quantum computer qubit readouts and radio astronomy. The developed compact models will be valid over both small and large-signal operation and will accurately model RF noise parameters. Current CMOS RF models are validated only down to -40C. However, there is strong interest in the development of CMOS circuits for cryogenic operation (4.2K) for applications such as qubit readouts for quantum computing and radio astronomy applications, particularly space-based radio telescopes. In this project, we will fabricate and demonstrate of a cryogenic CMOS low-noise amplifier operating in the band 2-3GHz. Cryogenic CMOS technology will also be used to demonstrate a low phase noise 10GHz oscillator and phase locked loop (PLL). In order to realise our technical deliverables, our team will fabricate discrete CMOS FETs using a maskset which allows complete deembedding of the intrinsic FET S-parameters from the surrounding structures such as probe pads and protection diodes. On-wafer calibration kits will be included as well as separate protection diodes and pads structures to allow determination of intrinsic FET S-parameters vs. bias and temperature.

* Information listed above is at the time of submission. *

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