Using Next Generation Processors

Award Information
Agency:
Department of Defense
Branch
Air Force
Amount:
$99,907.00
Award Year:
2008
Program:
SBIR
Phase:
Phase I
Contract:
FA8750-08-C-0052
Agency Tracking Number:
F073-018-1120
Solicitation Year:
2007
Solicitation Topic Code:
AF073-018
Solicitation Number:
2007.3
Small Business Information
MAXENTRIC TECHNOLOGIES LLC
2071 Lemoine Avenue Suite 302, Fort Lee, NJ, 07024
Hubzone Owned:
N
Socially and Economically Disadvantaged:
N
Woman Owned:
N
Duns:
145051095
Principal Investigator:
Houman Ghajari
Project Manager
(858) 272-8800
houman@maxentric.com
Business Contact:
Kamran Mahbobi
Managing Director
(201) 242-9805
kmahbobi@maxentric.com
Research Institution:
n/a
Abstract
Next generation processors attain better performance than existing microprocessors because the abstraction layers better expose the underlying VLSI resources (transistors, wires, pins, ...) and constraints (e.g., wire delay, power, ...). However, the management of these resources and constraints requires the development of more sophisticated hardware and software mechanisms, both to improve efficiency and to ease programmer burden. MaXentric believes the largest advances in the next decade of computer architecture will center around these mechanisms. Our vision is a tool chain of software support that helps the user parallelize applications from choosing the appropriate architecture to analyzing and profiling the application for potential re-organization and improvement. We propose one piece of this chain, codenamed PAMM (Problem-Architecture Mapping for Multi-core) that helps the user select an architecture for a given application and to make optimizations based on that architecture. Phase I efforts will establish a categorization of architectures and high performance problems, benchmark their relationships, and begin the design of the PAMM tool.

* information listed above is at the time of submission.

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