MICROCOMPUTER-NETWORK ARCHITECTURE FOR RANGE INSTRUMENTATION APPLICATIONS

Award Information
Agency: Department of Defense
Branch: Army
Contract: N/A
Agency Tracking Number: 5645
Amount: $439,548.00
Phase: Phase II
Program: SBIR
Awards Year: 1989
Solicitation Year: N/A
Solicitation Topic Code: N/A
Solicitation Number: N/A
Small Business Information
Mentor Technologies Inc.
318 Wall St Ste 2b, Kingston, NY, 12401
DUNS: N/A
HUBZone Owned: N
Woman Owned: N
Socially and Economically Disadvantaged: N
Principal Investigator
 Dr Mitchell R Belzer
 () -
Business Contact
Phone: () -
Research Institution
N/A
Abstract
VLSI (VERY LARGE SCALE INTEGRATION) TECHNOLOGY HAS BEEN DEVELOPED TO THE POINT WHERE SPECIAL PURPOSE PROCESSORS MAY BE CONCATENATED TO FORM SUPERCOMPUTERS WITH FASTER THROUGHPUT RATES THAN UNI-PROCESSOR MACHINES. CHO, INC. PROPOSES TO DESIGN AND DEVELOP A MULTI-PROCESSOR COMPUTER ARCHITECTURE FOR REAL-TIME DIGITAL FILTERING OF MULTI-SENSOR TRACKING DATA. THE ARCHITECTURE WILL BE OPTIMIZED FOR IMPLEMENTATION OF THE DECENTRALIZED SQUARE ROOT INFORMATION FILTER (SRIF). PHASE I RESEARCH WILL DEMONSTRATE FEASIBILITY OF THE DECENTRALIZED SRIF AS A MEANS FOR SOLVING THE LINEAR LEAST SQUARES ESTIMATION PROBLEM IN DECENTRALIZED FORM. PHASE II RESEARCH WILL FOCUS UPON DEVELOPMENT AND TESTING OF A PROTOTYPE DEVICE.

* information listed above is at the time of submission.

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