MICROCOMPUTER-NETWORK ARCHITECTURE FOR RANGE INSTRUMENTATION APPLICATIONS

Award Information
Agency:
Department of Defense
Branch:
Army
Amount:
$439,548.00
Award Year:
1989
Program:
SBIR
Phase:
Phase II
Contract:
N/A
Agency Tracking Number:
5645
Solicitation Year:
N/A
Solicitation Topic Code:
N/A
Solicitation Number:
N/A
Small Business Information
Mentor Technologies Inc.
318 Wall St Ste 2b, Kingston, NY, 12401
Hubzone Owned:
N
Socially and Economically Disadvantaged:
N
Woman Owned:
N
Duns:
N/A
Principal Investigator
 Dr Mitchell R Belzer
 () -
Business Contact
Phone: () -
Research Institution
N/A
Abstract
VLSI (VERY LARGE SCALE INTEGRATION) TECHNOLOGY HAS BEEN DEVELOPED TO THE POINT WHERE SPECIAL PURPOSE PROCESSORS MAY BE CONCATENATED TO FORM SUPERCOMPUTERS WITH FASTER THROUGHPUT RATES THAN UNI-PROCESSOR MACHINES. CHO, INC. PROPOSES TO DESIGN AND DEVELOP A MULTI-PROCESSOR COMPUTER ARCHITECTURE FOR REAL-TIME DIGITAL FILTERING OF MULTI-SENSOR TRACKING DATA. THE ARCHITECTURE WILL BE OPTIMIZED FOR IMPLEMENTATION OF THE DECENTRALIZED SQUARE ROOT INFORMATION FILTER (SRIF). PHASE I RESEARCH WILL DEMONSTRATE FEASIBILITY OF THE DECENTRALIZED SRIF AS A MEANS FOR SOLVING THE LINEAR LEAST SQUARES ESTIMATION PROBLEM IN DECENTRALIZED FORM. PHASE II RESEARCH WILL FOCUS UPON DEVELOPMENT AND TESTING OF A PROTOTYPE DEVICE.

* information listed above is at the time of submission.

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