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Photonic Systolic Processor for High-Throughput Image Processing

Award Information
Agency: Department of Defense
Branch: Strategic Capabilities Office
Contract: HQ003422C0110
Agency Tracking Number: SCO2D-0086
Amount: $1,499,292.81
Phase: Phase II
Program: SBIR
Solicitation Topic Code: SCO213-003
Solicitation Number: 21.3
Timeline
Solicitation Year: 2021
Award Year: 2022
Award Start Date (Proposal Award Date): 2022-09-28
Award End Date (Contract End Date): 2024-09-27
Small Business Information
4425 Fortran Drive
San Jose, CA 95134-2300
United States
DUNS: 877452664
HUBZone Owned: No
Woman Owned: No
Socially and Economically Disadvantaged: No
Principal Investigator
 Dr. Behzad Moslehi
 (408) 565-9004
 bm@ifos.com
Business Contact
 Dr. Behzad Moslehi
Phone: (408) 565-9004
Email: bm@ifos.com
Research Institution
N/A
Abstract

Conventional image processing and target recognition capabilities are struggling to keep pace with the data collected by the plethora of existing deployed sensor suites. Future developments in Deep Neural Networks (DNN) depend on advances in hardware just as much as in software. However, electronic hardware accelerators have already been pushed to their limits in scalability. IFOS proposes a chip-scale photonic accelerator concept based on adaptation of proven optical signal processing techniques for photonic integrated circuit (IC) implementation as a Photonic Systolic Processor (PSP). Combined with invertible neural networks, a cutting edge DNN technique, the solution will provide robust automatic target recognition on high-resolution imagery. IFOS will fabricate and develop an engineering prototype and benchmark it against Google’s Cloud Tensor Processing Unit (TPU) service, representing the state of the art in neural-network inference. IFOS will use the engineering prototype to further define performance limits of the photonic accelerator architecture in terms of computational dimensionality, computing power in units of Tera Operations per Second (TOPS), and power efficiency as functions of the input data rate and matrix loading speed. Implementation of the accelerator architecture using photonic ICs will enable economical and reliable production at scale using the mature US-based semiconductor infrastructure.

* Information listed above is at the time of submission. *

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