Enhanced Dielectric Performance in Metal/Polymer Nanocomposites Deposited by CCVD

Award Information
Agency:
Department of Defense
Branch
Missile Defense Agency
Amount:
$70,000.00
Award Year:
2002
Program:
SBIR
Phase:
Phase I
Contract:
DTRA01-02-P-0163
Award Id:
59004
Agency Tracking Number:
02-0495
Solicitation Year:
n/a
Solicitation Topic Code:
n/a
Solicitation Number:
n/a
Small Business Information
5315 Peachtree Industrial Blvd, Atlanta, GA, 30341
Hubzone Owned:
N
Minority Owned:
N
Woman Owned:
N
Duns:
806337762
Principal Investigator:
ToddPolley
Project Leader
(678) 287-3913
tpolley@microcoating.com
Business Contact:
DavidMotley
Executive VP, Marketing
(678) 287-2445
dmotley@microcoating.com
Research Institute:
n/a
Abstract
"This STTR Phase I will study and utilize the dielectric properties of nanocomposites (metal nanoparticles in a polymer matrix). It is theorized that dipoles in the metal (when in an applied field) simulate a true dielectric. These artificial dielectricshave the potential to have high dielectric constants (>100) while maintaining the low temperature processability of polymers. These practical, high-capacitance materials (>20nF/cm2) have great potential as embedded capacitors. In addition, high energydensity (> 1 J/cc) capacitors are needed for temporary backup power and pulsed-power in missile defense and space applications. The patented CCVD is uniquely suited for the development of these materials and has been successfully utilized to deposit metalnanoparticles (<10nm), thin polymers (<10mm), and composites. By co-depositing the metal nanoparticles and polymer, CCVD enables high well-dispersed, particle loadings in a thin polymer composite. Also, the flexibility of the CCVD process will enablefaster development cycle, scaling to large substrates and continuous economically feasible production. By teaming with Dr. C. P. Wong (Georgia Tech PRC) and licensing related intellectual property from Georgia Tech, this project has an increased chance ofsuccess. These new materials are needed in order to meet the projected trends for electronic device miniaturization. Currently, the majority of the board surface is occupied by passive

* information listed above is at the time of submission.

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