Dual Chip Approach to Radiation Hardened Logic

Award Information
Agency:
Department of Defense
Branch
Air Force
Amount:
$99,977.00
Award Year:
2006
Program:
SBIR
Phase:
Phase I
Contract:
FA9453-06-M-0148
Award Id:
78964
Agency Tracking Number:
F061-256-4000
Solicitation Year:
n/a
Solicitation Topic Code:
n/a
Solicitation Number:
n/a
Small Business Information
4775 Centennial Avenue Suite 130, Colorado Springs, CO, 80919
Hubzone Owned:
N
Minority Owned:
N
Woman Owned:
N
Duns:
619085371
Principal Investigator:
David Mavis
Senior Design Engineer
(505) 507-0542
david.mavis@micro-rdc.com
Business Contact:
Joe Cuchiaro
President
(719) 531-0805
jcuchiaro@aol.com
Research Institute:
n/a
Abstract
We wish to offer users nearly ASIC density (20X higher logic density than FPGAs), yet allow them to develop their systems with off-the-shelf FPGA-based parts. The core idea is to use a new high-density non-rad-hard FPGA for development, and an electrically and timing equivalent, rad-hard by design (RHBD) Structured ASIC in the same package for flight. This is much like using commercial Actel FPGAs for development, and their rad-hard versions for flight. Users would develop their systems with our FPGAs, and later replace them with factory-programmed rad-hard structured ASICs for flight, with close to zero risk of conversion problems.

* information listed above is at the time of submission.

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