Dual Chip Approach to Radiation Hardened Logic

Award Information
Agency: Department of Defense
Branch: Air Force
Contract: FA9453-06-M-0148
Agency Tracking Number: F061-256-4000
Amount: $99,977.00
Phase: Phase I
Program: SBIR
Awards Year: 2006
Solicitation Year: 2006
Solicitation Topic Code: AF06-256
Solicitation Number: 2006.1
Small Business Information
4775 Centennial Avenue Suite 130, Colorado Springs, CO, 80919
DUNS: 619085371
HUBZone Owned: N
Woman Owned: N
Socially and Economically Disadvantaged: N
Principal Investigator
 David Mavis
 Senior Design Engineer
 (505) 507-0542
 david.mavis@micro-rdc.com
Business Contact
 Joe Cuchiaro
Title: President
Phone: (719) 531-0805
Email: jcuchiaro@aol.com
Research Institution
N/A
Abstract
We wish to offer users nearly ASIC density (20X higher logic density than FPGAs), yet allow them to develop their systems with off-the-shelf FPGA-based parts. The core idea is to use a new high-density non-rad-hard FPGA for development, and an electrically and timing equivalent, rad-hard by design (RHBD) Structured ASIC in the same package for flight. This is much like using commercial Actel FPGAs for development, and their rad-hard versions for flight. Users would develop their systems with our FPGAs, and later replace them with factory-programmed rad-hard structured ASICs for flight, with close to zero risk of conversion problems.

* Information listed above is at the time of submission. *

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