Novel Mitigation Techniques for Reconfigurable Computers for Space Based Applications

Award Information
Agency: Department of Defense
Branch: Air Force
Contract: FA9453-08-M-0096
Agency Tracking Number: F081-094-1085
Amount: $99,946.00
Phase: Phase I
Program: SBIR
Awards Year: 2008
Solicitation Year: 2008
Solicitation Topic Code: AF081-094
Solicitation Number: 2008.1
Small Business Information
4775 Centennial Avenue, Suite 130, Colorado Springs, CO, 80919
DUNS: 619085371
HUBZone Owned: N
Woman Owned: N
Socially and Economically Disadvantaged: N
Principal Investigator
 Keith Avery
 Principle Investigator
 (505) 294-1962
Business Contact
 Karen Van Cura
Title: Cheif Financial Officer
Phone: (719) 531-0805
Research Institution
Reconfigurable systems popularity for space-based applications has grown considerably due to their flexibility and the ability to multiplex in real time different hardware configurations based on the demand of the system application. Commercial FPGA based designs are susceptible to Single Event Upsets (SEUs) caused by radiated charged particles. This is primarily due to the use of a commercial SRAM based FPGA. The traditional approach for Single Event Upset (SEU) mitigation on commercial parts consists of triple modular redundancy (TMR). Although proven effective this method adds a certain amount of logic overhead and a penalty in power consumption and processing speed. A more recent approach - called “scrubbing” - relies on simply reloading the configuration memory frames at defined time intervals. This approach is possible in the case of FPGA devices that support partial reconfiguration, such as the Xilinx Virtex II, Spartan 3, Virtex 2-Pro, Virtex 4 and Virtex 5. We propose to investigate all previously enumerated considerations and alternatives to determine the best SEU mitigation technique. In Phase I of the effort, we will explore different scrubbing methods and define the scrubbing circuitry capabilities based on the architecture’s characteristics. This phase will also comprise the investigation of scrubbing rates required in this architecture for a number of representative applications. It will also provide us with the tools and framework to evaluate in the same way different reconfigurable computer architectures. BENEFIT: If a Phase II and Phase III options are exercised for this proposal the AFRL and other DoD systems will have access to a component that will reliably allow the use of commercial FPGAs for space applications. This new scrubber device will have the performance options that will allow it to provide scrubbing capability to a myriad of FPGA devices. If this goes forward, this new architecture will also include fault injection capability which will allow the user to synthetically test the mitigation technique against the simulated faults based on environmental requirements for the end application. This feature will reduce the need for radiation testing which is becoming increasingly difficult in new technologies and advanced systems. Using the Structured ASIC as the fabrication medium will make the scrubber inherently radiation hardened. Above the hardware benefits from the component development is the software simulation capability for benchmarking architectures and circuits. This will also provide a good demonstration of a reconfigurable computing architecture for use in high end computing applications.

* information listed above is at the time of submission.

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