Dual Chip Approach to Radiation Hardened Logic

Award Information
Agency:
Department of Defense
Branch
Air Force
Amount:
$1,490,524.00
Award Year:
2007
Program:
SBIR
Phase:
Phase II
Contract:
FA9453-07-C-0039
Award Id:
78964
Agency Tracking Number:
F061-256-4000
Solicitation Year:
n/a
Solicitation Topic Code:
n/a
Solicitation Number:
n/a
Small Business Information
4775 Centennial Avenue, Suite 130, Colorado Springs, CO, 80919
Hubzone Owned:
N
Minority Owned:
N
Woman Owned:
N
Duns:
619085371
Principal Investigator:
Patrick McGuirk
Principal Investigator
(505) 294-1962
patrick.mcguirk@micro-rdc.com
Business Contact:
Mary Dyson
Director Business Operati
(505) 294-1962
mary.dyson@micro-rdc.com
Research Institute:
n/a
Abstract
In an electronics system, the incorporation of reprogrammable logic, such as Field Programmable Gate Arrays (FPGAs), into the design can offer many benefits to a digital designer. For radiation hardened reprogrammable electronics, the choices among appropriate devices are very limited. AFRL is at the forefront of designing and developing high performance radiation hardened digital solutions. One such solution is the Via Programmable Gate Array (VPGA), which offers designers the high performance offered by a deep-submicron (90 nm) process, and the flexibility of reprogrammability with only one mask layer change. However, for a design engineer accustomed to working with COTS FPGAs engineers, the path to implementing the design into the VPGA is not trivial. A design methodology is proposed to ease this migration. This design approach will facilitate the transferal of FPGA designs to VPGA designs. As an option to this proposal, we offer to design, manufacture, and test four flight designs crucial to the development of the Plug-n-Play Satellite (PnPSat). Because these designs are predominantly FPGA based, the option can serve as a springboard to VPGA implementations of these designs.

* information listed above is at the time of submission.

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