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Enhanced Architecture for Direct Digital Synthesizer (DDS) Designs

Award Information
Agency: Department of Defense
Branch: Army
Contract: N/A
Agency Tracking Number: 20571
Amount: $50,000.00
Phase: Phase I
Program: SBIR
Solicitation Topic Code: N/A
Solicitation Number: N/A
Timeline
Solicitation Year: N/A
Award Year: 1993
Award Start Date (Proposal Award Date): N/A
Award End Date (Contract End Date): N/A
Small Business Information
300 31st St. No. Suite 238
St. Petersburg, FL 33713
United States
DUNS: N/A
HUBZone Owned: No
Woman Owned: No
Socially and Economically Disadvantaged: No
Principal Investigator
 Cesar E. Alvarez, Jr.
 (813) 327-8676
Business Contact
Phone: () -
Research Institution
N/A
Abstract

The proposed research is in the area of new architectures for a Direct Digital Synthesizer (DDS). Current DDS architecturs employ a phase acumulator, incremented each sample clock by a phase increment word. By controlling this word the rate (frequency) at which the accumulator overflows is controlled. The result is a stable programmable frequency source. The accumulator phase information is applied to a ROM in order to convert the phase information into a digitized in order to convert the phase information into a digitized sine waveform. The digitized wave is applied to a D/A converter and a low pass filter to generate the final waveform. Due to finite word lengths and the physical limitations of the architecture, phase and amplitude noise spurs are introduced during this process. Increasing the word lengths can reduce the noise spurs by about 6 db. per bit. What is proposes is two innovations that could reduce the noise spurs by more than 6db. per bit and thereby enhance the spectral purity of the generated waveform. To accomplish this the research proposes the use of: 1) New number systems with certain more desirable properties. 2) Approximation theory involving reduced computad computations.

* Information listed above is at the time of submission. *

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