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Development of a Radiation Hardened Wafer Scale Signal Processor
Title: Principal Investigator
Phone: (505) 768-7788
Title: Director of Contracts
Phone: (805) 963-8761
The development of a radiation hardened WSSP (Wafer Scale Signal Processor) is proposed. The project will result in a high performance, programmable, floating point dual processor. Radiation hardening will be designed for environments including totalionizing dose (>300 Krad(Si)), dose rate upset (>1011 rad(Si)/s), latchup (immune to both dose rate and single event latchup), and single event effects (<1x10^-10 errors per bit day). The WSSP is specifically designed for fault tolerance and powerefficient, sustained floating point performance. It is optimized for efficient memory utilization with each of the dual processing elements capable of accessing either of two independent memory banks over two 72 bit (64 bits plus byte parity) buses. TheWSSP can perform 8 single precision floating point operations per clock cycle. The Phase 1 effort will result in a high level partitioning of the rad hard design into synthesizeable macros. A series of analyses will be performed to demonstrate theability to achieve hardness required for strategic systems. The detailed design and fabrication of the RH-WSSP in a state-of-the-art SOI process will be performed in Phase 2.A radiation hardened WSSP will provide an enabling technology for highperformance, digital signal processing in space. The WSSP is optimized for MFLOPS/Watt, which is the critical metric for the floating point intensive applications encountered in next generation space systems.
* Information listed above is at the time of submission. *