Hybrid CMOS/Nanodevice Integrated Circuits - Design and Fabrication

Award Information
Agency:
Department of Defense
Branch
Air Force
Amount:
$99,937.00
Award Year:
2007
Program:
STTR
Phase:
Phase I
Contract:
FA9550-07-C-0125
Award Id:
83362
Agency Tracking Number:
F074-025-0277
Solicitation Year:
n/a
Solicitation Topic Code:
n/a
Solicitation Number:
n/a
Small Business Information
1807-C West Braker Lane, Suite 100, Austin, TX, 78758
Hubzone Owned:
N
Minority Owned:
N
Woman Owned:
N
Duns:
039398891
Principal Investigator:
Doug Resnick
Vice President
(512) 339-7760
dresnick@molecularimprints.com
Business Contact:
Dave Gino
Chief Financial Officer
(512) 334-1209
dgino@molecularimprints.com
Research Institute:
SUNY, STONY BROOK
Konstantin Likharev
Dept. of Physics and Astronomy
Stony Brook, NY, 11794
(631) 632-8159
Nonprofit college or university
Abstract
This proposal will investigate fabrication of CMOL devices (CMOS/nanowire/MOLecular hybrids) using fabrication processes that have commercial viability. These circuits are one of the most promising approaches for continued device scaling well below 10nm. Such circuits combine a semiconductor transistors system with a nanowire crossbar, with simple two-terminal nanodevices self-assembled at each crosspoint. The proposed research is an inter-disciplinary effort that brings together the expertise in nanofabrication at Molecular Imprints, Inc., and hybrid circuit design expertise at SUNY, Stony Brook. Device architectures that are specifically suited for ease of integration of the nanowire cross-bars with their CMOS counterparts are studied. Also, these devices are designed to be tolerant to defects and alignment errors during the integration of nano-wires with CMOS. A novel nanofabrication process that includes imprint lithography in conjunction with a reverse tone etch process is proposed. This process allows for fabrication of nanowires over pre-existing topography. This is critical in fabricating fault-tolerant interconnections between the nanowire cross-bars and the underlying CMOS circuitry.

* information listed above is at the time of submission.

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